// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other 
// applicable license agreement, including, without limitation, 
// that your use is for the sole purpose of programming logic 
// devices manufactured by Intel and sold by Intel or its 
// authorized distributors.  Please refer to the applicable 
// agreement for further details.


// 
// Device: Altera EP4CE22F17C6 Package FBGA256
// 

//
// This file contains Slow Corner delays for the design using part EP4CE22F17C6,
// with speed grade 6, core voltage 1.2VmV, and temperature 85 Celsius
//

// 
// This SDF file should be used for ModelSim-Altera (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "DE0_NANO")
  (DATE "08/09/2018 00:24:51")
  (VENDOR "Altera")
  (PROGRAM "Quartus Prime")
  (VERSION "Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[0\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1306:1306:1306) (1313:1313:1313))
        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[1\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1306:1306:1306) (1313:1313:1313))
        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[5\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2953:2953:2953) (3020:3020:3020))
        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[7\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2342:2342:2342) (2441:2441:2441))
        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[9\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2999:2999:2999) (3098:3098:3098))
        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[11\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2131:2131:2131) (2190:2190:2190))
        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[13\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2482:2482:2482) (2551:2551:2551))
        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[15\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2008:2008:2008) (2080:2080:2080))
        (IOPATH i o (4557:4557:4557) (4190:4190:4190))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[17\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (2404:2404:2404) (2548:2548:2548))
        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[19\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1623:1623:1623) (1703:1703:1703))
        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[21\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1888:1888:1888) (1911:1911:1911))
        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0_D\[23\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1553:1553:1553) (1614:1614:1614))
        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE CLOCK_50\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (479:479:479) (732:732:732))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_pll")
    (INSTANCE PLL_inst\|altpll_component\|auto_generated\|pll1)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (1878:1878:1878) (1878:1878:1878))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE PLL_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (1896:1896:1896) (1878:1878:1878))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE PLL_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (1896:1896:1896) (1878:1878:1878))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[0\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (282:282:282) (379:379:379))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[1\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT datab (289:289:289) (380:380:380))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[2\]\~14)
    (DELAY
      (ABSOLUTE
        (PORT datab (293:293:293) (386:386:386))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[0\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT datab (272:272:272) (356:356:356))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (694:694:694) (756:756:756))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[1\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT dataa (273:273:273) (364:364:364))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (694:694:694) (756:756:756))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[2\]\~14)
    (DELAY
      (ABSOLUTE
        (PORT dataa (273:273:273) (363:363:363))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (694:694:694) (756:756:756))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[3\]\~16)
    (DELAY
      (ABSOLUTE
        (PORT datab (272:272:272) (358:358:358))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (694:694:694) (756:756:756))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[4\]\~18)
    (DELAY
      (ABSOLUTE
        (PORT dataa (411:411:411) (494:494:494))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (694:694:694) (756:756:756))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[5\]\~20)
    (DELAY
      (ABSOLUTE
        (PORT datab (281:281:281) (369:369:369))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (694:694:694) (756:756:756))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[6\]\~22)
    (DELAY
      (ABSOLUTE
        (PORT datab (279:279:279) (367:367:367))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (694:694:694) (756:756:756))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[7\]\~24)
    (DELAY
      (ABSOLUTE
        (PORT dataa (301:301:301) (394:394:394))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (694:694:694) (756:756:756))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[8\]\~26)
    (DELAY
      (ABSOLUTE
        (PORT dataa (416:416:416) (499:499:499))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (694:694:694) (756:756:756))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|pixel_count\[9\]\~28)
    (DELAY
      (ABSOLUTE
        (PORT dataa (283:283:283) (374:374:374))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH cin combout (455:455:455) (437:437:437))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|pixel_count\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1530:1530:1530) (1544:1544:1544))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (694:694:694) (756:756:756))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|Equal0\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (420:420:420) (501:501:501))
        (PORT datab (271:271:271) (356:356:356))
        (PORT datac (252:252:252) (336:336:336))
        (PORT datad (245:245:245) (317:317:317))
        (IOPATH dataa combout (301:301:301) (299:299:299))
        (IOPATH datab combout (300:300:300) (308:308:308))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|Equal0\~2)
    (DELAY
      (ABSOLUTE
        (PORT datac (245:245:245) (325:325:325))
        (PORT datad (247:247:247) (321:321:321))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|Equal0\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (411:411:411) (495:495:495))
        (PORT datab (279:279:279) (368:368:368))
        (PORT datac (271:271:271) (356:356:356))
        (PORT datad (252:252:252) (328:328:328))
        (IOPATH dataa combout (350:350:350) (366:366:366))
        (IOPATH datab combout (344:344:344) (369:369:369))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE KEY\[0\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (481:481:481) (733:733:733))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[9\]\~17)
    (DELAY
      (ABSOLUTE
        (PORT dataa (203:203:203) (248:248:248))
        (PORT datab (199:199:199) (238:238:238))
        (PORT datac (175:175:175) (209:209:209))
        (PORT datad (3368:3368:3368) (3665:3665:3665))
        (IOPATH dataa combout (300:300:300) (307:307:307))
        (IOPATH datab combout (300:300:300) (310:310:310))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1525:1525:1525) (1538:1538:1538))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1136:1136:1136) (1185:1185:1185))
        (PORT ena (1438:1438:1438) (1426:1426:1426))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[3\]\~18)
    (DELAY
      (ABSOLUTE
        (PORT datab (296:296:296) (391:391:391))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1525:1525:1525) (1538:1538:1538))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1136:1136:1136) (1185:1185:1185))
        (PORT ena (1438:1438:1438) (1426:1426:1426))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[4\]\~20)
    (DELAY
      (ABSOLUTE
        (PORT datab (264:264:264) (347:347:347))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1525:1525:1525) (1538:1538:1538))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1136:1136:1136) (1185:1185:1185))
        (PORT ena (1438:1438:1438) (1426:1426:1426))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[5\]\~22)
    (DELAY
      (ABSOLUTE
        (PORT dataa (266:266:266) (352:352:352))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1525:1525:1525) (1538:1538:1538))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1136:1136:1136) (1185:1185:1185))
        (PORT ena (1438:1438:1438) (1426:1426:1426))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[6\]\~24)
    (DELAY
      (ABSOLUTE
        (PORT datab (263:263:263) (345:345:345))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1525:1525:1525) (1538:1538:1538))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1136:1136:1136) (1185:1185:1185))
        (PORT ena (1438:1438:1438) (1426:1426:1426))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[7\]\~26)
    (DELAY
      (ABSOLUTE
        (PORT dataa (265:265:265) (351:351:351))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1525:1525:1525) (1538:1538:1538))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1136:1136:1136) (1185:1185:1185))
        (PORT ena (1438:1438:1438) (1426:1426:1426))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[8\]\~28)
    (DELAY
      (ABSOLUTE
        (PORT datab (270:270:270) (354:354:354))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1525:1525:1525) (1538:1538:1538))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1136:1136:1136) (1185:1185:1185))
        (PORT ena (1438:1438:1438) (1426:1426:1426))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[9\]\~30)
    (DELAY
      (ABSOLUTE
        (PORT dataa (274:274:274) (363:363:363))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH cin combout (455:455:455) (437:437:437))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1525:1525:1525) (1538:1538:1538))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1136:1136:1136) (1185:1185:1185))
        (PORT ena (1438:1438:1438) (1426:1426:1426))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|_\~1)
    (DELAY
      (ABSOLUTE
        (PORT datac (623:623:623) (675:675:675))
        (PORT datad (604:604:604) (659:659:659))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|Equal1\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (690:690:690) (749:749:749))
        (PORT datac (617:617:617) (671:671:671))
        (PORT datad (597:597:597) (649:649:649))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|Equal1\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (643:643:643) (716:716:716))
        (PORT datab (636:636:636) (705:705:705))
        (PORT datac (620:620:620) (677:677:677))
        (PORT datad (182:182:182) (211:211:211))
        (IOPATH dataa combout (300:300:300) (307:307:307))
        (IOPATH datab combout (300:300:300) (311:311:311))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|_\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (631:631:631) (712:712:712))
        (PORT datad (592:592:592) (651:651:651))
        (IOPATH dataa combout (325:325:325) (328:328:328))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|line_count\[9\]\~16)
    (DELAY
      (ABSOLUTE
        (PORT dataa (345:345:345) (385:385:385))
        (PORT datab (199:199:199) (239:239:239))
        (PORT datac (173:173:173) (207:207:207))
        (PORT datad (3555:3555:3555) (3900:3900:3900))
        (IOPATH dataa combout (304:304:304) (299:299:299))
        (IOPATH datab combout (333:333:333) (332:332:332))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1525:1525:1525) (1538:1538:1538))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1136:1136:1136) (1185:1185:1185))
        (PORT ena (1438:1438:1438) (1426:1426:1426))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE driver\|line_count\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1525:1525:1525) (1538:1538:1538))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1136:1136:1136) (1185:1185:1185))
        (PORT ena (1438:1438:1438) (1426:1426:1426))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|V_SYNC_NEG\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (627:627:627) (710:710:710))
        (PORT datab (639:639:639) (700:700:700))
        (PORT datac (619:619:619) (679:679:679))
        (PORT datad (598:598:598) (653:653:653))
        (IOPATH dataa combout (324:324:324) (328:328:328))
        (IOPATH datab combout (333:333:333) (332:332:332))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|V_SYNC_NEG\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (641:641:641) (713:713:713))
        (PORT datab (691:691:691) (752:752:752))
        (PORT datac (618:618:618) (673:673:673))
        (PORT datad (590:590:590) (649:649:649))
        (IOPATH dataa combout (337:337:337) (338:338:338))
        (IOPATH datab combout (331:331:331) (342:342:342))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|V_SYNC_NEG\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (201:201:201) (245:245:245))
        (PORT datab (198:198:198) (237:237:237))
        (PORT datac (619:619:619) (674:674:674))
        (IOPATH dataa combout (354:354:354) (349:349:349))
        (IOPATH datab combout (355:355:355) (349:349:349))
        (IOPATH datac combout (243:243:243) (242:242:242))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|H_SYNC_NEG\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (413:413:413) (493:493:493))
        (PORT datab (281:281:281) (369:369:369))
        (PORT datac (273:273:273) (358:358:358))
        (PORT datad (254:254:254) (330:330:330))
        (IOPATH dataa combout (337:337:337) (338:338:338))
        (IOPATH datab combout (337:337:337) (348:348:348))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|H_SYNC_NEG\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (419:419:419) (503:503:503))
        (PORT datab (196:196:196) (235:235:235))
        (PORT datac (253:253:253) (338:338:338))
        (IOPATH dataa combout (341:341:341) (319:319:319))
        (IOPATH datab combout (342:342:342) (318:318:318))
        (IOPATH datac combout (241:241:241) (241:241:241))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[9\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (631:631:631) (706:706:706))
        (PORT datab (474:474:474) (551:551:551))
        (PORT datac (623:623:623) (687:687:687))
        (PORT datad (446:446:446) (525:525:525))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[8\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (633:633:633) (708:708:708))
        (PORT datab (477:477:477) (554:554:554))
        (PORT datac (626:626:626) (688:688:688))
        (PORT datad (448:448:448) (526:526:526))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[7\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (629:629:629) (701:701:701))
        (PORT datab (472:472:472) (548:548:548))
        (PORT datac (624:624:624) (686:686:686))
        (PORT datad (444:444:444) (522:522:522))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|_\~2)
    (DELAY
      (ABSOLUTE
        (PORT datab (298:298:298) (392:392:392))
        (PORT datad (268:268:268) (346:346:346))
        (IOPATH datab combout (306:306:306) (311:311:311))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[10\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT datab (297:297:297) (391:391:391))
        (PORT datac (258:258:258) (343:343:343))
        (PORT datad (267:267:267) (346:346:346))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[6\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (629:629:629) (701:701:701))
        (PORT datab (481:481:481) (562:562:562))
        (PORT datac (624:624:624) (686:686:686))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datac combout (243:243:243) (242:242:242))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[5\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT datac (624:624:624) (685:685:685))
        (PORT datad (445:445:445) (522:522:522))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[9\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (279:279:279) (372:372:372))
        (PORT datab (295:295:295) (390:390:390))
        (PORT datac (258:258:258) (343:343:343))
        (PORT datad (266:266:266) (347:347:347))
        (IOPATH dataa combout (341:341:341) (367:367:367))
        (IOPATH datab combout (344:344:344) (369:369:369))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[8\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (279:279:279) (372:372:372))
        (PORT datab (296:296:296) (389:389:389))
        (PORT datac (258:258:258) (343:343:343))
        (PORT datad (266:266:266) (347:347:347))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH datab combout (355:355:355) (349:349:349))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (343:343:343) (381:381:381))
        (PORT datab (635:635:635) (686:686:686))
        (IOPATH dataa combout (339:339:339) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (344:344:344) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (200:200:200) (243:243:243))
        (PORT datab (515:515:515) (532:532:532))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (344:344:344) (382:382:382))
        (PORT datab (199:199:199) (238:238:238))
        (IOPATH dataa combout (354:354:354) (349:349:349))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (355:355:355) (349:349:349))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (201:201:201) (244:244:244))
        (PORT datab (377:377:377) (402:402:402))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~8)
    (DELAY
      (ABSOLUTE
        (PORT datab (197:197:197) (236:236:236))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~10)
    (DELAY
      (ABSOLUTE
        (PORT datab (198:198:198) (238:238:238))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[2\]\[5\]\~8)
    (DELAY
      (ABSOLUTE
        (PORT datac (243:243:243) (325:325:325))
        (PORT datad (246:246:246) (318:318:318))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (632:632:632) (686:686:686))
        (PORT datab (345:345:345) (379:379:379))
        (IOPATH dataa combout (339:339:339) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (344:344:344) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (560:560:560) (575:575:575))
        (PORT datab (517:517:517) (528:528:528))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[7\]\~9)
    (DELAY
      (ABSOLUTE
        (PORT dataa (628:628:628) (711:711:711))
        (PORT datab (667:667:667) (726:726:726))
        (PORT datac (605:605:605) (670:670:670))
        (PORT datad (591:591:591) (651:651:651))
        (IOPATH dataa combout (337:337:337) (347:347:347))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[6\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (631:631:631) (707:707:707))
        (PORT datac (606:606:606) (668:668:668))
        (PORT datad (590:590:590) (647:647:647))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[0\]\[5\]\~11)
    (DELAY
      (ABSOLUTE
        (PORT datac (606:606:606) (669:669:669))
        (PORT datad (604:604:604) (664:664:664))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (694:694:694) (780:780:780))
        (PORT datab (635:635:635) (696:696:696))
        (IOPATH dataa combout (339:339:339) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (344:344:344) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (369:369:369) (389:389:389))
        (PORT datab (714:714:714) (797:797:797))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (682:682:682) (780:780:780))
        (PORT datab (336:336:336) (360:360:360))
        (IOPATH dataa combout (354:354:354) (349:349:349))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (355:355:355) (349:349:349))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (371:371:371) (394:394:394))
        (PORT datab (706:706:706) (797:797:797))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~8)
    (DELAY
      (ABSOLUTE
        (PORT dataa (346:346:346) (384:384:384))
        (PORT datab (703:703:703) (792:792:792))
        (IOPATH dataa combout (354:354:354) (349:349:349))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (355:355:355) (349:349:349))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (384:384:384) (411:411:411))
        (PORT datab (682:682:682) (776:776:776))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~12)
    (DELAY
      (ABSOLUTE
        (PORT dataa (345:345:345) (384:384:384))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~14)
    (DELAY
      (ABSOLUTE
        (PORT datab (377:377:377) (402:402:402))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~16)
    (DELAY
      (ABSOLUTE
        (PORT datab (200:200:200) (239:239:239))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~18)
    (DELAY
      (ABSOLUTE
        (PORT datab (200:200:200) (239:239:239))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|address_reg_b\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1525:1525:1525) (1539:1539:1539))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[32\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (481:481:481) (733:733:733))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[33\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (481:481:481) (733:733:733))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pixel_data_RGB332\[0\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datac (244:244:244) (323:323:323))
        (PORT datad (3031:3031:3031) (3301:3301:3301))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE is_lsb\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (196:196:196) (222:222:222))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE is_lsb)
    (DELAY
      (ABSOLUTE
        (PORT clk (1748:1748:1748) (1794:1794:1794))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[0\]\~15)
    (DELAY
      (ABSOLUTE
        (PORT dataa (431:431:431) (496:496:496))
        (PORT datab (989:989:989) (1078:1078:1078))
        (IOPATH dataa combout (339:339:339) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (344:344:344) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE last_href\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (3030:3030:3030) (3301:3301:3301))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE last_href)
    (DELAY
      (ABSOLUTE
        (PORT clk (1748:1748:1748) (1794:1794:1794))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[30\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (481:481:481) (733:733:733))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[13\]\~43)
    (DELAY
      (ABSOLUTE
        (PORT datab (274:274:274) (360:360:360))
        (PORT datac (3084:3084:3084) (3351:3351:3351))
        (PORT datad (3025:3025:3025) (3296:3296:3296))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1768:1768:1768) (1798:1798:1798))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (3924:3924:3924) (3678:3678:3678))
        (PORT ena (1492:1492:1492) (1498:1498:1498))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[1\]\~17)
    (DELAY
      (ABSOLUTE
        (PORT datab (262:262:262) (344:344:344))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1768:1768:1768) (1798:1798:1798))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (3924:3924:3924) (3678:3678:3678))
        (PORT ena (1492:1492:1492) (1498:1498:1498))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[2\]\~19)
    (DELAY
      (ABSOLUTE
        (PORT dataa (264:264:264) (351:351:351))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1768:1768:1768) (1798:1798:1798))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (3924:3924:3924) (3678:3678:3678))
        (PORT ena (1492:1492:1492) (1498:1498:1498))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[3\]\~21)
    (DELAY
      (ABSOLUTE
        (PORT datab (263:263:263) (345:345:345))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1768:1768:1768) (1798:1798:1798))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (3924:3924:3924) (3678:3678:3678))
        (PORT ena (1492:1492:1492) (1498:1498:1498))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[4\]\~23)
    (DELAY
      (ABSOLUTE
        (PORT dataa (265:265:265) (353:353:353))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1768:1768:1768) (1798:1798:1798))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (3924:3924:3924) (3678:3678:3678))
        (PORT ena (1492:1492:1492) (1498:1498:1498))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[5\]\~25)
    (DELAY
      (ABSOLUTE
        (PORT dataa (265:265:265) (353:353:353))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1768:1768:1768) (1798:1798:1798))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (3924:3924:3924) (3678:3678:3678))
        (PORT ena (1492:1492:1492) (1498:1498:1498))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[6\]\~27)
    (DELAY
      (ABSOLUTE
        (PORT datab (264:264:264) (347:347:347))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1768:1768:1768) (1798:1798:1798))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (3924:3924:3924) (3678:3678:3678))
        (PORT ena (1492:1492:1492) (1498:1498:1498))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[7\]\~29)
    (DELAY
      (ABSOLUTE
        (PORT datab (264:264:264) (347:347:347))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1768:1768:1768) (1798:1798:1798))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (3924:3924:3924) (3678:3678:3678))
        (PORT ena (1492:1492:1492) (1498:1498:1498))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[8\]\~31)
    (DELAY
      (ABSOLUTE
        (PORT datab (264:264:264) (347:347:347))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1768:1768:1768) (1798:1798:1798))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (3924:3924:3924) (3678:3678:3678))
        (PORT ena (1492:1492:1492) (1498:1498:1498))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[9\]\~33)
    (DELAY
      (ABSOLUTE
        (PORT datab (264:264:264) (347:347:347))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1768:1768:1768) (1798:1798:1798))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (3924:3924:3924) (3678:3678:3678))
        (PORT ena (1492:1492:1492) (1498:1498:1498))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[10\]\~35)
    (DELAY
      (ABSOLUTE
        (PORT dataa (266:266:266) (352:352:352))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1768:1768:1768) (1798:1798:1798))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (3924:3924:3924) (3678:3678:3678))
        (PORT ena (1492:1492:1492) (1498:1498:1498))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[11\]\~37)
    (DELAY
      (ABSOLUTE
        (PORT datab (263:263:263) (345:345:345))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1768:1768:1768) (1798:1798:1798))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (3924:3924:3924) (3678:3678:3678))
        (PORT ena (1492:1492:1492) (1498:1498:1498))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[12\]\~39)
    (DELAY
      (ABSOLUTE
        (PORT dataa (265:265:265) (351:351:351))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[12\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1768:1768:1768) (1798:1798:1798))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (3924:3924:3924) (3678:3678:3678))
        (PORT ena (1492:1492:1492) (1498:1498:1498))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[13\]\~41)
    (DELAY
      (ABSOLUTE
        (PORT datab (263:263:263) (345:345:345))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[13\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1768:1768:1768) (1798:1798:1798))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (3924:3924:3924) (3678:3678:3678))
        (PORT ena (1492:1492:1492) (1498:1498:1498))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[0\]\~15)
    (DELAY
      (ABSOLUTE
        (PORT dataa (912:912:912) (1000:1000:1000))
        (PORT datab (289:289:289) (380:380:380))
        (IOPATH dataa combout (339:339:339) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (344:344:344) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE always0\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (272:272:272) (358:358:358))
        (PORT datac (3083:3083:3083) (3349:3349:3349))
        (PORT datad (3026:3026:3026) (3296:3296:3296))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1712:1712:1712) (1751:1751:1751))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1075:1075:1075) (1154:1154:1154))
        (PORT ena (3972:3972:3972) (3671:3671:3671))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[1\]\~17)
    (DELAY
      (ABSOLUTE
        (PORT datab (301:301:301) (397:397:397))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1712:1712:1712) (1751:1751:1751))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1075:1075:1075) (1154:1154:1154))
        (PORT ena (3972:3972:3972) (3671:3671:3671))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[2\]\~19)
    (DELAY
      (ABSOLUTE
        (PORT dataa (302:302:302) (407:407:407))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1712:1712:1712) (1751:1751:1751))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1075:1075:1075) (1154:1154:1154))
        (PORT ena (3972:3972:3972) (3671:3671:3671))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[3\]\~21)
    (DELAY
      (ABSOLUTE
        (PORT datab (296:296:296) (389:389:389))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1712:1712:1712) (1751:1751:1751))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1075:1075:1075) (1154:1154:1154))
        (PORT ena (3972:3972:3972) (3671:3671:3671))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[4\]\~23)
    (DELAY
      (ABSOLUTE
        (PORT dataa (266:266:266) (353:353:353))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1712:1712:1712) (1751:1751:1751))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1075:1075:1075) (1154:1154:1154))
        (PORT ena (3972:3972:3972) (3671:3671:3671))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[5\]\~25)
    (DELAY
      (ABSOLUTE
        (PORT dataa (266:266:266) (353:353:353))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1712:1712:1712) (1751:1751:1751))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1075:1075:1075) (1154:1154:1154))
        (PORT ena (3972:3972:3972) (3671:3671:3671))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[6\]\~27)
    (DELAY
      (ABSOLUTE
        (PORT datab (264:264:264) (347:347:347))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1712:1712:1712) (1751:1751:1751))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1075:1075:1075) (1154:1154:1154))
        (PORT ena (3972:3972:3972) (3671:3671:3671))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[7\]\~29)
    (DELAY
      (ABSOLUTE
        (PORT datab (264:264:264) (347:347:347))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1712:1712:1712) (1751:1751:1751))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1075:1075:1075) (1154:1154:1154))
        (PORT ena (3972:3972:3972) (3671:3671:3671))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[9\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (702:702:702) (778:778:778))
        (PORT datab (700:700:700) (766:766:766))
        (PORT datac (677:677:677) (740:740:740))
        (PORT datad (694:694:694) (759:759:759))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[8\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (704:704:704) (778:778:778))
        (PORT datab (702:702:702) (765:765:765))
        (PORT datac (678:678:678) (741:741:741))
        (PORT datad (693:693:693) (757:757:757))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH datab combout (355:355:355) (349:349:349))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|_\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (709:709:709) (768:768:768))
        (PORT datac (692:692:692) (747:747:747))
        (IOPATH datab combout (342:342:342) (342:342:342))
        (IOPATH datac combout (243:243:243) (242:242:242))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[7\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (703:703:703) (776:776:776))
        (PORT datab (701:701:701) (765:765:765))
        (PORT datac (678:678:678) (741:741:741))
        (PORT datad (693:693:693) (758:758:758))
        (IOPATH dataa combout (354:354:354) (349:349:349))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[6\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (703:703:703) (777:777:777))
        (PORT datac (671:671:671) (733:733:733))
        (PORT datad (693:693:693) (759:759:759))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[10\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT datab (296:296:296) (388:388:388))
        (PORT datac (275:275:275) (367:367:367))
        (PORT datad (275:275:275) (366:366:366))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[9\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (300:300:300) (404:404:404))
        (PORT datab (292:292:292) (386:386:386))
        (PORT datac (270:270:270) (360:360:360))
        (PORT datad (261:261:261) (340:340:340))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[5\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (715:715:715) (776:776:776))
        (PORT datad (693:693:693) (757:757:757))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[8\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (305:305:305) (412:412:412))
        (PORT datab (297:297:297) (393:393:393))
        (PORT datac (277:277:277) (368:368:368))
        (PORT datad (269:269:269) (350:350:350))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH datab combout (355:355:355) (349:349:349))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (736:736:736) (809:809:809))
        (PORT datab (632:632:632) (649:649:649))
        (IOPATH dataa combout (339:339:339) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (344:344:344) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (632:632:632) (647:647:647))
        (PORT datab (198:198:198) (237:237:237))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (200:200:200) (244:244:244))
        (PORT datab (634:634:634) (650:650:650))
        (IOPATH dataa combout (354:354:354) (349:349:349))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (355:355:355) (349:349:349))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (635:635:635) (652:652:652))
        (PORT datab (199:199:199) (238:238:238))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~8)
    (DELAY
      (ABSOLUTE
        (PORT datab (199:199:199) (239:239:239))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~10)
    (DELAY
      (ABSOLUTE
        (PORT datab (199:199:199) (237:237:237))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[8\]\~31)
    (DELAY
      (ABSOLUTE
        (PORT datab (264:264:264) (347:347:347))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1712:1712:1712) (1751:1751:1751))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1075:1075:1075) (1154:1154:1154))
        (PORT ena (3972:3972:3972) (3671:3671:3671))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[9\]\~33)
    (DELAY
      (ABSOLUTE
        (PORT datab (264:264:264) (348:348:348))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1712:1712:1712) (1751:1751:1751))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1075:1075:1075) (1154:1154:1154))
        (PORT ena (3972:3972:3972) (3671:3671:3671))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[2\]\[5\])
    (DELAY
      (ABSOLUTE
        (PORT datac (976:976:976) (1036:1036:1036))
        (PORT datad (976:976:976) (1041:1041:1041))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (674:674:674) (752:752:752))
        (PORT datab (197:197:197) (235:235:235))
        (IOPATH dataa combout (339:339:339) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (344:344:344) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (199:199:199) (242:242:242))
        (PORT datab (338:338:338) (369:369:369))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[7\]\~8)
    (DELAY
      (ABSOLUTE
        (PORT dataa (306:306:306) (413:413:413))
        (PORT datab (297:297:297) (393:393:393))
        (PORT datac (278:278:278) (369:369:369))
        (PORT datad (269:269:269) (348:348:348))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[6\]\~9)
    (DELAY
      (ABSOLUTE
        (PORT dataa (307:307:307) (414:414:414))
        (PORT datac (278:278:278) (369:369:369))
        (PORT datad (270:270:270) (349:349:349))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[0\]\[5\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT datac (687:687:687) (750:750:750))
        (PORT datad (662:662:662) (719:719:719))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (725:725:725) (790:790:790))
        (PORT datab (669:669:669) (719:719:719))
        (IOPATH dataa combout (339:339:339) (367:367:367))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (344:344:344) (369:369:369))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (436:436:436) (496:496:496))
        (PORT datab (197:197:197) (236:236:236))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (617:617:617) (650:650:650))
        (PORT datab (638:638:638) (699:699:699))
        (IOPATH dataa combout (354:354:354) (349:349:349))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (355:355:355) (349:349:349))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (406:406:406) (474:474:474))
        (PORT datab (677:677:677) (694:694:694))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~8)
    (DELAY
      (ABSOLUTE
        (PORT dataa (671:671:671) (733:733:733))
        (PORT datab (375:375:375) (401:401:401))
        (IOPATH dataa combout (354:354:354) (349:349:349))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (355:355:355) (349:349:349))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (589:589:589) (598:598:598))
        (PORT datab (432:432:432) (490:490:490))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~12)
    (DELAY
      (ABSOLUTE
        (PORT dataa (678:678:678) (730:730:730))
        (PORT datab (338:338:338) (371:371:371))
        (IOPATH dataa combout (354:354:354) (349:349:349))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (355:355:355) (349:349:349))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~14)
    (DELAY
      (ABSOLUTE
        (PORT dataa (679:679:679) (732:732:732))
        (PORT datab (376:376:376) (401:401:401))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~16)
    (DELAY
      (ABSOLUTE
        (PORT dataa (439:439:439) (500:500:500))
        (PORT datab (557:557:557) (573:573:573))
        (IOPATH dataa combout (354:354:354) (349:349:349))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (355:355:355) (349:349:349))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~18)
    (DELAY
      (ABSOLUTE
        (PORT dataa (634:634:634) (686:686:686))
        (PORT datab (342:342:342) (376:376:376))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH dataa cout (436:436:436) (315:315:315))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datab cout (446:446:446) (318:318:318))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
        (IOPATH cin cout (58:58:58) (58:58:58))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE X_ADDR\[14\]\~44)
    (DELAY
      (ABSOLUTE
        (PORT dataa (266:266:266) (353:353:353))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH cin combout (455:455:455) (437:437:437))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE X_ADDR\[14\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1768:1768:1768) (1798:1798:1798))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (3924:3924:3924) (3678:3678:3678))
        (PORT ena (1492:1492:1492) (1498:1498:1498))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Y_ADDR\[10\]\~35)
    (DELAY
      (ABSOLUTE
        (PORT dataa (267:267:267) (354:354:354))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH cin combout (455:455:455) (437:437:437))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE Y_ADDR\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1712:1712:1712) (1751:1751:1751))
        (PORT d (74:74:74) (91:91:91))
        (PORT sclr (1075:1075:1075) (1154:1154:1154))
        (PORT ena (3972:3972:3972) (3671:3671:3671))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD sclr (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[2\]\[6\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT datab (1010:1010:1010) (1080:1080:1080))
        (PORT datac (972:972:972) (1035:1035:1035))
        (PORT datad (956:956:956) (1014:1014:1014))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|romout\[1\]\[10\]\~11)
    (DELAY
      (ABSOLUTE
        (PORT dataa (699:699:699) (778:778:778))
        (PORT datac (676:676:676) (741:741:741))
        (PORT datad (672:672:672) (731:731:731))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~12)
    (DELAY
      (ABSOLUTE
        (PORT datad (174:174:174) (199:199:199))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (618:618:618) (647:647:647))
        (PORT datad (172:172:172) (198:198:198))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add0\~20)
    (DELAY
      (ABSOLUTE
        (PORT datab (394:394:394) (459:459:459))
        (PORT datad (527:527:527) (537:537:537))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE W_EN\~0)
    (DELAY
      (ABSOLUTE
        (PORT datac (247:247:247) (327:327:327))
        (PORT datad (3026:3026:3026) (3296:3296:3296))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE W_EN\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (198:198:198) (224:224:224))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE W_EN)
    (DELAY
      (ABSOLUTE
        (PORT clk (1748:1748:1748) (1794:1794:1794))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|decode2\|w_anode300w\[2\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (223:223:223) (271:271:271))
        (PORT datac (194:194:194) (238:238:238))
        (PORT datad (949:949:949) (1028:1028:1028))
        (IOPATH datab combout (336:336:336) (325:325:325))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE PLL_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[2\]\~clkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (1896:1896:1896) (1878:1878:1878))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|romout\[1\]\[10\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT datab (472:472:472) (549:549:549))
        (PORT datac (598:598:598) (663:663:663))
        (PORT datad (445:445:445) (522:522:522))
        (IOPATH datab combout (355:355:355) (369:369:369))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~12)
    (DELAY
      (ABSOLUTE
        (PORT datad (174:174:174) (200:200:200))
        (IOPATH datad combout (130:130:130) (120:120:120))
        (IOPATH cin combout (455:455:455) (437:437:437))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Mult1\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (338:338:338) (373:373:373))
        (PORT datab (378:378:378) (401:401:401))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH cin combout (455:455:455) (437:437:437))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Add3\~20)
    (DELAY
      (ABSOLUTE
        (PORT datab (200:200:200) (239:239:239))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH cin combout (455:455:455) (437:437:437))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|rden_decode_b\|w_anode338w\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (376:376:376) (406:406:406))
        (PORT datad (368:368:368) (393:393:393))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[27\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (481:481:481) (733:733:733))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pixel_data_RGB332\[7\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (3383:3383:3383) (3642:3642:3642))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (2033:2033:2033) (2099:2099:2099))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (1241:1241:1241) (1250:1250:1250))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1727:1727:1727) (1886:1886:1886))
        (PORT clk (1851:1851:1851) (1879:1879:1879))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1945:1945:1945) (2050:2050:2050))
        (PORT d[1] (2649:2649:2649) (2916:2916:2916))
        (PORT d[2] (3014:3014:3014) (3199:3199:3199))
        (PORT d[3] (1269:1269:1269) (1343:1343:1343))
        (PORT d[4] (1691:1691:1691) (1744:1744:1744))
        (PORT d[5] (1101:1101:1101) (1121:1121:1121))
        (PORT d[6] (1564:1564:1564) (1656:1656:1656))
        (PORT d[7] (2666:2666:2666) (2775:2775:2775))
        (PORT d[8] (1368:1368:1368) (1385:1385:1385))
        (PORT d[9] (1392:1392:1392) (1406:1406:1406))
        (PORT d[10] (1425:1425:1425) (1439:1439:1439))
        (PORT d[11] (3164:3164:3164) (3251:3251:3251))
        (PORT d[12] (1960:1960:1960) (2038:2038:2038))
        (PORT clk (1848:1848:1848) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2492:2492:2492) (2515:2515:2515))
        (PORT clk (1848:1848:1848) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1851:1851:1851) (1879:1879:1879))
        (PORT d[0] (3017:3017:3017) (3052:3052:3052))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1880:1880:1880))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1787:1787:1787) (1870:1870:1870))
        (PORT d[1] (1567:1567:1567) (1675:1675:1675))
        (PORT d[2] (1531:1531:1531) (1635:1635:1635))
        (PORT d[3] (1569:1569:1569) (1675:1675:1675))
        (PORT d[4] (2081:2081:2081) (2133:2133:2133))
        (PORT d[5] (2229:2229:2229) (2270:2270:2270))
        (PORT d[6] (1908:1908:1908) (1977:1977:1977))
        (PORT d[7] (2078:2078:2078) (2200:2200:2200))
        (PORT d[8] (2212:2212:2212) (2273:2273:2273))
        (PORT d[9] (1762:1762:1762) (1839:1839:1839))
        (PORT d[10] (1966:1966:1966) (2030:2030:2030))
        (PORT d[11] (1747:1747:1747) (1825:1825:1825))
        (PORT d[12] (1785:1785:1785) (1862:1862:1862))
        (PORT clk (1812:1812:1812) (1806:1806:1806))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1812:1812:1812) (1806:1806:1806))
        (PORT d[0] (1636:1636:1636) (1686:1686:1686))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1813:1813:1813) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1813:1813:1813) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a7.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1813:1813:1813) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|decode2\|w_anode313w\[2\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (226:226:226) (275:275:275))
        (PORT datac (198:198:198) (241:241:241))
        (PORT datad (950:950:950) (1028:1028:1028))
        (IOPATH datab combout (304:304:304) (311:311:311))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|rden_decode_b\|w_anode352w\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (376:376:376) (406:406:406))
        (PORT datad (368:368:368) (393:393:393))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1463:1463:1463) (1586:1586:1586))
        (PORT clk (1852:1852:1852) (1879:1879:1879))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2288:2288:2288) (2415:2415:2415))
        (PORT d[1] (2644:2644:2644) (2908:2908:2908))
        (PORT d[2] (3015:3015:3015) (3169:3169:3169))
        (PORT d[3] (1302:1302:1302) (1388:1388:1388))
        (PORT d[4] (1388:1388:1388) (1442:1442:1442))
        (PORT d[5] (1147:1147:1147) (1182:1182:1182))
        (PORT d[6] (1272:1272:1272) (1337:1337:1337))
        (PORT d[7] (1449:1449:1449) (1469:1469:1469))
        (PORT d[8] (1127:1127:1127) (1148:1148:1148))
        (PORT d[9] (1930:1930:1930) (2004:2004:2004))
        (PORT d[10] (1176:1176:1176) (1197:1197:1197))
        (PORT d[11] (2813:2813:2813) (2893:2893:2893))
        (PORT d[12] (1952:1952:1952) (2014:2014:2014))
        (PORT clk (1849:1849:1849) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2547:2547:2547) (2531:2531:2531))
        (PORT clk (1849:1849:1849) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1879:1879:1879))
        (PORT d[0] (3072:3072:3072) (3068:3068:3068))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1853:1853:1853) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1853:1853:1853) (1880:1880:1880))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1853:1853:1853) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1853:1853:1853) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1523:1523:1523) (1613:1613:1613))
        (PORT d[1] (1293:1293:1293) (1401:1401:1401))
        (PORT d[2] (1858:1858:1858) (1984:1984:1984))
        (PORT d[3] (1895:1895:1895) (2028:2028:2028))
        (PORT d[4] (2342:2342:2342) (2409:2409:2409))
        (PORT d[5] (2261:2261:2261) (2317:2317:2317))
        (PORT d[6] (1925:1925:1925) (2007:2007:2007))
        (PORT d[7] (1602:1602:1602) (1676:1676:1676))
        (PORT d[8] (2461:2461:2461) (2551:2551:2551))
        (PORT d[9] (2300:2300:2300) (2405:2405:2405))
        (PORT d[10] (2448:2448:2448) (2503:2503:2503))
        (PORT d[11] (1460:1460:1460) (1539:1539:1539))
        (PORT d[12] (2024:2024:2024) (2128:2128:2128))
        (PORT clk (1813:1813:1813) (1806:1806:1806))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1813:1813:1813) (1806:1806:1806))
        (PORT d[0] (1658:1658:1658) (1697:1697:1697))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1814:1814:1814) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1814:1814:1814) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a15.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1814:1814:1814) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|address_reg_b\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1525:1525:1525) (1539:1539:1539))
        (PORT d (74:74:74) (91:91:91))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[7\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1257:1257:1257) (1360:1360:1360))
        (PORT datab (933:933:933) (1006:1006:1006))
        (PORT datac (1128:1128:1128) (1143:1143:1143))
        (PORT datad (986:986:986) (1075:1075:1075))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH datab combout (355:355:355) (349:349:349))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|decode2\|w_anode321w\[2\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (224:224:224) (269:269:269))
        (PORT datac (195:195:195) (236:236:236))
        (PORT datad (952:952:952) (1034:1034:1034))
        (IOPATH datab combout (333:333:333) (332:332:332))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|rden_decode_b\|w_anode361w\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (192:192:192) (225:225:225))
        (PORT datad (194:194:194) (219:219:219))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1481:1481:1481) (1606:1606:1606))
        (PORT clk (1851:1851:1851) (1879:1879:1879))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1640:1640:1640) (1750:1750:1750))
        (PORT d[1] (2353:2353:2353) (2594:2594:2594))
        (PORT d[2] (2982:2982:2982) (3157:3157:3157))
        (PORT d[3] (1334:1334:1334) (1444:1444:1444))
        (PORT d[4] (1411:1411:1411) (1478:1478:1478))
        (PORT d[5] (1163:1163:1163) (1221:1221:1221))
        (PORT d[6] (1293:1293:1293) (1363:1363:1363))
        (PORT d[7] (2359:2359:2359) (2443:2443:2443))
        (PORT d[8] (1164:1164:1164) (1209:1209:1209))
        (PORT d[9] (1953:1953:1953) (2031:2031:2031))
        (PORT d[10] (1186:1186:1186) (1227:1227:1227))
        (PORT d[11] (2831:2831:2831) (2907:2907:2907))
        (PORT d[12] (1694:1694:1694) (1745:1745:1745))
        (PORT clk (1848:1848:1848) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2182:2182:2182) (2240:2240:2240))
        (PORT clk (1848:1848:1848) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1851:1851:1851) (1879:1879:1879))
        (PORT d[0] (2707:2707:2707) (2777:2777:2777))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1880:1880:1880))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1475:1475:1475) (1547:1547:1547))
        (PORT d[1] (1878:1878:1878) (2012:2012:2012))
        (PORT d[2] (1882:1882:1882) (1980:1980:1980))
        (PORT d[3] (1885:1885:1885) (1994:1994:1994))
        (PORT d[4] (2372:2372:2372) (2452:2452:2452))
        (PORT d[5] (2250:2250:2250) (2321:2321:2321))
        (PORT d[6] (1962:1962:1962) (2069:2069:2069))
        (PORT d[7] (2066:2066:2066) (2155:2155:2155))
        (PORT d[8] (2496:2496:2496) (2599:2599:2599))
        (PORT d[9] (2050:2050:2050) (2165:2165:2165))
        (PORT d[10] (2489:2489:2489) (2567:2567:2567))
        (PORT d[11] (2046:2046:2046) (2162:2162:2162))
        (PORT d[12] (2030:2030:2030) (2137:2137:2137))
        (PORT clk (1812:1812:1812) (1806:1806:1806))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1812:1812:1812) (1806:1806:1806))
        (PORT d[0] (1309:1309:1309) (1319:1319:1319))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1813:1813:1813) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1813:1813:1813) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a23.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1813:1813:1813) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|decode2\|w_anode329w\[2\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (224:224:224) (270:270:270))
        (PORT datac (195:195:195) (236:236:236))
        (PORT datad (952:952:952) (1034:1034:1034))
        (IOPATH datab combout (306:306:306) (308:308:308))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|rden_decode_b\|w_anode370w\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (374:374:374) (403:403:403))
        (PORT datad (366:366:366) (390:390:390))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[23\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (481:481:481) (733:733:733))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pixel_data_RGB332\[0\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (3120:3120:3120) (3390:3390:3390))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1998:1998:1998) (2050:2050:2050))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (1277:1277:1277) (1304:1304:1304))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[24\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (481:481:481) (733:733:733))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pixel_data_RGB332\[1\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (3233:3233:3233) (3487:3487:3487))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1998:1998:1998) (2050:2050:2050))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (1277:1277:1277) (1304:1304:1304))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[20\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (481:481:481) (733:733:733))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (2033:2033:2033) (2099:2099:2099))
        (PORT asdata (3711:3711:3711) (3998:3998:3998))
        (PORT ena (1241:1241:1241) (1250:1250:1250))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD asdata (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[21\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (481:481:481) (733:733:733))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (2033:2033:2033) (2099:2099:2099))
        (PORT asdata (3420:3420:3420) (3697:3697:3697))
        (PORT ena (1241:1241:1241) (1250:1250:1250))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD asdata (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[22\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (479:479:479) (732:732:732))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pixel_data_RGB332\[4\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (3421:3421:3421) (3780:3780:3780))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (2033:2033:2033) (2099:2099:2099))
        (PORT d (74:74:74) (91:91:91))
        (PORT ena (1241:1241:1241) (1250:1250:1250))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[25\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (479:479:479) (732:732:732))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (2033:2033:2033) (2099:2099:2099))
        (PORT asdata (3664:3664:3664) (4009:4009:4009))
        (PORT ena (1241:1241:1241) (1250:1250:1250))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD asdata (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO_1_D\[26\]\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (481:481:481) (733:733:733))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pixel_data_RGB332\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (2033:2033:2033) (2099:2099:2099))
        (PORT asdata (3433:3433:3433) (3707:3707:3707))
        (PORT ena (1241:1241:1241) (1250:1250:1250))
        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
      )
    )
    (TIMINGCHECK
      (HOLD asdata (posedge clk) (157:157:157))
      (HOLD ena (posedge clk) (157:157:157))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1041:1041:1041) (1101:1101:1101))
        (PORT d[1] (985:985:985) (1051:1051:1051))
        (PORT d[2] (1000:1000:1000) (1060:1060:1060))
        (PORT d[3] (1267:1267:1267) (1364:1364:1364))
        (PORT d[4] (1300:1300:1300) (1364:1364:1364))
        (PORT d[5] (1000:1000:1000) (1065:1065:1065))
        (PORT d[6] (1302:1302:1302) (1360:1360:1360))
        (PORT d[7] (971:971:971) (1029:1029:1029))
        (PORT clk (1858:1858:1858) (1884:1884:1884))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1472:1472:1472) (1534:1534:1534))
        (PORT d[1] (1889:1889:1889) (2010:2010:2010))
        (PORT d[2] (1321:1321:1321) (1406:1406:1406))
        (PORT d[3] (1849:1849:1849) (1954:1954:1954))
        (PORT d[4] (1253:1253:1253) (1339:1339:1339))
        (PORT d[5] (2622:2622:2622) (2790:2790:2790))
        (PORT d[6] (2271:2271:2271) (2394:2394:2394))
        (PORT d[7] (2400:2400:2400) (2527:2527:2527))
        (PORT d[8] (1430:1430:1430) (1505:1505:1505))
        (PORT d[9] (1346:1346:1346) (1391:1391:1391))
        (PORT clk (1855:1855:1855) (1880:1880:1880))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1475:1475:1475) (1449:1449:1449))
        (PORT clk (1855:1855:1855) (1880:1880:1880))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1858:1858:1858) (1884:1884:1884))
        (PORT d[0] (2000:2000:2000) (1986:1986:1986))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1859:1859:1859) (1885:1885:1885))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1859:1859:1859) (1885:1885:1885))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1859:1859:1859) (1885:1885:1885))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1859:1859:1859) (1885:1885:1885))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1789:1789:1789) (1847:1847:1847))
        (PORT d[1] (1535:1535:1535) (1597:1597:1597))
        (PORT d[2] (1224:1224:1224) (1289:1289:1289))
        (PORT d[3] (1486:1486:1486) (1583:1583:1583))
        (PORT d[4] (1162:1162:1162) (1164:1164:1164))
        (PORT d[5] (2216:2216:2216) (2266:2266:2266))
        (PORT d[6] (2585:2585:2585) (2682:2682:2682))
        (PORT d[7] (1133:1133:1133) (1177:1177:1177))
        (PORT d[8] (2322:2322:2322) (2374:2374:2374))
        (PORT d[9] (2044:2044:2044) (2150:2150:2150))
        (PORT clk (1819:1819:1819) (1811:1811:1811))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1819:1819:1819) (1811:1811:1811))
        (PORT d[0] (784:784:784) (742:742:742))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1820:1820:1820) (1812:1812:1812))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1820:1820:1820) (1812:1812:1812))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a24.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1820:1820:1820) (1812:1812:1812))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[7\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1260:1260:1260) (1367:1367:1367))
        (PORT datab (1020:1020:1020) (1106:1106:1106))
        (PORT datac (822:822:822) (827:827:827))
        (PORT datad (1102:1102:1102) (1112:1112:1112))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH datab combout (342:342:342) (318:318:318))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[7\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (697:697:697) (795:795:795))
        (PORT datac (619:619:619) (674:674:674))
        (PORT datad (598:598:598) (656:656:656))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE LessThan0\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (682:682:682) (777:777:777))
        (PORT datab (714:714:714) (796:796:796))
        (PORT datac (658:658:658) (740:740:740))
        (PORT datad (678:678:678) (757:757:757))
        (IOPATH dataa combout (304:304:304) (308:308:308))
        (IOPATH datab combout (306:306:306) (308:308:308))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[7\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (201:201:201) (245:245:245))
        (PORT datab (208:208:208) (249:249:249))
        (PORT datac (622:622:622) (680:680:680))
        (PORT datad (319:319:319) (338:338:338))
        (IOPATH dataa combout (354:354:354) (367:367:367))
        (IOPATH datab combout (331:331:331) (342:342:342))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[7\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1174:1174:1174) (1265:1265:1265))
        (PORT datab (198:198:198) (237:237:237))
        (PORT datac (170:170:170) (203:203:203))
        (PORT datad (1094:1094:1094) (1137:1137:1137))
        (IOPATH dataa combout (325:325:325) (328:328:328))
        (IOPATH datab combout (304:304:304) (308:308:308))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2028:2028:2028) (2114:2114:2114))
        (PORT clk (1850:1850:1850) (1878:1878:1878))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1976:1976:1976) (2071:2071:2071))
        (PORT d[1] (2344:2344:2344) (2580:2580:2580))
        (PORT d[2] (2667:2667:2667) (2831:2831:2831))
        (PORT d[3] (1608:1608:1608) (1723:1723:1723))
        (PORT d[4] (1702:1702:1702) (1780:1780:1780))
        (PORT d[5] (1453:1453:1453) (1534:1534:1534))
        (PORT d[6] (1999:1999:1999) (2129:2129:2129))
        (PORT d[7] (2042:2042:2042) (2122:2122:2122))
        (PORT d[8] (1429:1429:1429) (1481:1481:1481))
        (PORT d[9] (1841:1841:1841) (1882:1882:1882))
        (PORT d[10] (1474:1474:1474) (1537:1537:1537))
        (PORT d[11] (2492:2492:2492) (2543:2543:2543))
        (PORT d[12] (2265:2265:2265) (2420:2420:2420))
        (PORT clk (1847:1847:1847) (1874:1874:1874))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2189:2189:2189) (2195:2195:2195))
        (PORT clk (1847:1847:1847) (1874:1874:1874))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1850:1850:1850) (1878:1878:1878))
        (PORT d[0] (2715:2715:2715) (2735:2735:2735))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1851:1851:1851) (1879:1879:1879))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1851:1851:1851) (1879:1879:1879))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1851:1851:1851) (1879:1879:1879))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1851:1851:1851) (1879:1879:1879))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2154:2154:2154) (2240:2240:2240))
        (PORT d[1] (1629:1629:1629) (1764:1764:1764))
        (PORT d[2] (2175:2175:2175) (2295:2295:2295))
        (PORT d[3] (2176:2176:2176) (2304:2304:2304))
        (PORT d[4] (2646:2646:2646) (2738:2738:2738))
        (PORT d[5] (2556:2556:2556) (2633:2633:2633))
        (PORT d[6] (2289:2289:2289) (2423:2423:2423))
        (PORT d[7] (1301:1301:1301) (1331:1331:1331))
        (PORT d[8] (2833:2833:2833) (2939:2939:2939))
        (PORT d[9] (2384:2384:2384) (2503:2503:2503))
        (PORT d[10] (2741:2741:2741) (2809:2809:2809))
        (PORT d[11] (2364:2364:2364) (2481:2481:2481))
        (PORT d[12] (1210:1210:1210) (1271:1271:1271))
        (PORT clk (1811:1811:1811) (1805:1805:1805))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1811:1811:1811) (1805:1805:1805))
        (PORT d[0] (1961:1961:1961) (2030:2030:2030))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1812:1812:1812) (1806:1806:1806))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1812:1812:1812) (1806:1806:1806))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a14.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1812:1812:1812) (1806:1806:1806))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2298:2298:2298) (2377:2377:2377))
        (PORT clk (1849:1849:1849) (1876:1876:1876))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1974:1974:1974) (2077:2077:2077))
        (PORT d[1] (2064:2064:2064) (2288:2288:2288))
        (PORT d[2] (2662:2662:2662) (2823:2823:2823))
        (PORT d[3] (1639:1639:1639) (1771:1771:1771))
        (PORT d[4] (1714:1714:1714) (1805:1805:1805))
        (PORT d[5] (1427:1427:1427) (1503:1503:1503))
        (PORT d[6] (2480:2480:2480) (2621:2621:2621))
        (PORT d[7] (2059:2059:2059) (2136:2136:2136))
        (PORT d[8] (1487:1487:1487) (1560:1560:1560))
        (PORT d[9] (1903:1903:1903) (1953:1953:1953))
        (PORT d[10] (1478:1478:1478) (1544:1544:1544))
        (PORT d[11] (2514:2514:2514) (2563:2563:2563))
        (PORT d[12] (2320:2320:2320) (2479:2479:2479))
        (PORT clk (1846:1846:1846) (1872:1872:1872))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2150:2150:2150) (2168:2168:2168))
        (PORT clk (1846:1846:1846) (1872:1872:1872))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1849:1849:1849) (1876:1876:1876))
        (PORT d[0] (2675:2675:2675) (2705:2705:2705))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1850:1850:1850) (1877:1877:1877))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1850:1850:1850) (1877:1877:1877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1850:1850:1850) (1877:1877:1877))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1850:1850:1850) (1877:1877:1877))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1840:1840:1840) (1905:1905:1905))
        (PORT d[1] (2174:2174:2174) (2288:2288:2288))
        (PORT d[2] (2154:2154:2154) (2272:2272:2272))
        (PORT d[3] (1923:1923:1923) (2025:2025:2025))
        (PORT d[4] (2674:2674:2674) (2774:2774:2774))
        (PORT d[5] (2542:2542:2542) (2619:2619:2619))
        (PORT d[6] (2241:2241:2241) (2345:2345:2345))
        (PORT d[7] (1867:1867:1867) (1891:1891:1891))
        (PORT d[8] (2807:2807:2807) (2909:2909:2909))
        (PORT d[9] (2390:2390:2390) (2511:2511:2511))
        (PORT d[10] (2745:2745:2745) (2819:2819:2819))
        (PORT d[11] (2350:2350:2350) (2490:2490:2490))
        (PORT d[12] (1233:1233:1233) (1296:1296:1296))
        (PORT clk (1810:1810:1810) (1803:1803:1803))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1810:1810:1810) (1803:1803:1803))
        (PORT d[0] (1030:1030:1030) (1012:1012:1012))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1811:1811:1811) (1804:1804:1804))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1811:1811:1811) (1804:1804:1804))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a6.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1811:1811:1811) (1804:1804:1804))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[6\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1254:1254:1254) (1359:1359:1359))
        (PORT datab (677:677:677) (687:687:687))
        (PORT datac (901:901:901) (925:925:925))
        (PORT datad (987:987:987) (1069:1069:1069))
        (IOPATH dataa combout (339:339:339) (367:367:367))
        (IOPATH datab combout (344:344:344) (369:369:369))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1491:1491:1491) (1556:1556:1556))
        (PORT clk (1843:1843:1843) (1871:1871:1871))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2255:2255:2255) (2367:2367:2367))
        (PORT d[1] (2284:2284:2284) (2478:2478:2478))
        (PORT d[2] (2364:2364:2364) (2486:2486:2486))
        (PORT d[3] (1896:1896:1896) (2028:2028:2028))
        (PORT d[4] (1981:1981:1981) (2073:2073:2073))
        (PORT d[5] (1793:1793:1793) (1881:1881:1881))
        (PORT d[6] (2227:2227:2227) (2379:2379:2379))
        (PORT d[7] (2041:2041:2041) (2092:2092:2092))
        (PORT d[8] (1707:1707:1707) (1777:1777:1777))
        (PORT d[9] (1906:1906:1906) (1962:1962:1962))
        (PORT d[10] (1773:1773:1773) (1858:1858:1858))
        (PORT d[11] (1685:1685:1685) (1719:1719:1719))
        (PORT d[12] (2017:2017:2017) (2159:2159:2159))
        (PORT clk (1840:1840:1840) (1867:1867:1867))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1916:1916:1916) (1973:1973:1973))
        (PORT clk (1840:1840:1840) (1867:1867:1867))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1843:1843:1843) (1871:1871:1871))
        (PORT d[0] (2440:2440:2440) (2510:2510:2510))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1844:1844:1844) (1872:1872:1872))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1844:1844:1844) (1872:1872:1872))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1844:1844:1844) (1872:1872:1872))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1844:1844:1844) (1872:1872:1872))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1793:1793:1793) (1858:1858:1858))
        (PORT d[1] (1295:1295:1295) (1402:1402:1402))
        (PORT d[2] (2087:2087:2087) (2183:2183:2183))
        (PORT d[3] (1320:1320:1320) (1436:1436:1436))
        (PORT d[4] (2941:2941:2941) (3039:3039:3039))
        (PORT d[5] (3150:3150:3150) (3258:3258:3258))
        (PORT d[6] (2592:2592:2592) (2697:2697:2697))
        (PORT d[7] (1169:1169:1169) (1204:1204:1204))
        (PORT d[8] (3135:3135:3135) (3262:3262:3262))
        (PORT d[9] (2722:2722:2722) (2847:2847:2847))
        (PORT d[10] (3032:3032:3032) (3104:3104:3104))
        (PORT d[11] (2619:2619:2619) (2772:2772:2772))
        (PORT d[12] (1185:1185:1185) (1222:1222:1222))
        (PORT clk (1804:1804:1804) (1798:1798:1798))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1804:1804:1804) (1798:1798:1798))
        (PORT d[0] (769:769:769) (753:753:753))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1805:1805:1805) (1799:1799:1799))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1805:1805:1805) (1799:1799:1799))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a22.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1805:1805:1805) (1799:1799:1799))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[6\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1260:1260:1260) (1361:1361:1361))
        (PORT datab (1019:1019:1019) (1108:1108:1108))
        (PORT datac (618:618:618) (644:644:644))
        (PORT datad (1055:1055:1055) (1060:1060:1060))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH datab combout (342:342:342) (318:318:318))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[6\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (200:200:200) (245:245:245))
        (PORT datab (200:200:200) (239:239:239))
        (PORT datac (1144:1144:1144) (1231:1231:1231))
        (PORT datad (1093:1093:1093) (1142:1142:1142))
        (IOPATH dataa combout (303:303:303) (299:299:299))
        (IOPATH datab combout (304:304:304) (308:308:308))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1548:1548:1548) (1654:1654:1654))
        (PORT clk (1851:1851:1851) (1879:1879:1879))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1936:1936:1936) (2042:2042:2042))
        (PORT d[1] (2349:2349:2349) (2587:2587:2587))
        (PORT d[2] (2710:2710:2710) (2868:2868:2868))
        (PORT d[3] (1294:1294:1294) (1401:1401:1401))
        (PORT d[4] (1408:1408:1408) (1477:1477:1477))
        (PORT d[5] (1167:1167:1167) (1228:1228:1228))
        (PORT d[6] (2030:2030:2030) (2168:2168:2168))
        (PORT d[7] (1428:1428:1428) (1453:1453:1453))
        (PORT d[8] (1170:1170:1170) (1220:1220:1220))
        (PORT d[9] (1925:1925:1925) (1980:1980:1980))
        (PORT d[10] (1191:1191:1191) (1237:1237:1237))
        (PORT d[11] (2774:2774:2774) (2802:2802:2802))
        (PORT d[12] (1144:1144:1144) (1202:1202:1202))
        (PORT clk (1848:1848:1848) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2174:2174:2174) (2176:2176:2176))
        (PORT clk (1848:1848:1848) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1851:1851:1851) (1879:1879:1879))
        (PORT d[0] (2699:2699:2699) (2713:2713:2713))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1880:1880:1880))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2167:2167:2167) (2237:2237:2237))
        (PORT d[1] (1621:1621:1621) (1748:1748:1748))
        (PORT d[2] (1851:1851:1851) (1958:1958:1958))
        (PORT d[3] (2189:2189:2189) (2303:2303:2303))
        (PORT d[4] (2373:2373:2373) (2453:2453:2453))
        (PORT d[5] (2279:2279:2279) (2360:2360:2360))
        (PORT d[6] (1967:1967:1967) (2079:2079:2079))
        (PORT d[7] (1608:1608:1608) (1671:1671:1671))
        (PORT d[8] (2492:2492:2492) (2593:2593:2593))
        (PORT d[9] (2056:2056:2056) (2173:2173:2173))
        (PORT d[10] (2516:2516:2516) (2595:2595:2595))
        (PORT d[11] (2025:2025:2025) (2139:2139:2139))
        (PORT d[12] (2302:2302:2302) (2404:2404:2404))
        (PORT clk (1812:1812:1812) (1806:1806:1806))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1812:1812:1812) (1806:1806:1806))
        (PORT d[0] (1302:1302:1302) (1288:1288:1288))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1813:1813:1813) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1813:1813:1813) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a5.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1813:1813:1813) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1844:1844:1844) (1944:1944:1944))
        (PORT clk (1851:1851:1851) (1879:1879:1879))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1957:1957:1957) (2078:2078:2078))
        (PORT d[1] (2326:2326:2326) (2563:2563:2563))
        (PORT d[2] (2667:2667:2667) (2832:2832:2832))
        (PORT d[3] (1567:1567:1567) (1660:1660:1660))
        (PORT d[4] (1441:1441:1441) (1517:1517:1517))
        (PORT d[5] (1141:1141:1141) (1198:1198:1198))
        (PORT d[6] (2030:2030:2030) (2167:2167:2167))
        (PORT d[7] (2043:2043:2043) (2123:2123:2123))
        (PORT d[8] (1143:1143:1143) (1190:1190:1190))
        (PORT d[9] (1918:1918:1918) (1971:1971:1971))
        (PORT d[10] (1192:1192:1192) (1238:1238:1238))
        (PORT d[11] (2520:2520:2520) (2575:2575:2575))
        (PORT d[12] (1524:1524:1524) (1598:1598:1598))
        (PORT clk (1848:1848:1848) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2226:2226:2226) (2190:2190:2190))
        (PORT clk (1848:1848:1848) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1851:1851:1851) (1879:1879:1879))
        (PORT d[0] (2751:2751:2751) (2727:2727:2727))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1880:1880:1880))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2166:2166:2166) (2230:2230:2230))
        (PORT d[1] (1636:1636:1636) (1761:1761:1761))
        (PORT d[2] (2170:2170:2170) (2286:2286:2286))
        (PORT d[3] (2219:2219:2219) (2331:2331:2331))
        (PORT d[4] (2057:2057:2057) (2134:2134:2134))
        (PORT d[5] (2280:2280:2280) (2362:2362:2362))
        (PORT d[6] (2253:2253:2253) (2364:2364:2364))
        (PORT d[7] (1197:1197:1197) (1247:1247:1247))
        (PORT d[8] (2793:2793:2793) (2912:2912:2912))
        (PORT d[9] (2349:2349:2349) (2482:2482:2482))
        (PORT d[10] (2759:2759:2759) (2819:2819:2819))
        (PORT d[11] (2336:2336:2336) (2457:2457:2457))
        (PORT d[12] (2309:2309:2309) (2414:2414:2414))
        (PORT clk (1812:1812:1812) (1806:1806:1806))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1812:1812:1812) (1806:1806:1806))
        (PORT d[0] (1651:1651:1651) (1712:1712:1712))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1813:1813:1813) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1813:1813:1813) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a13.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1813:1813:1813) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[5\]\~8)
    (DELAY
      (ABSOLUTE
        (PORT dataa (677:677:677) (717:717:717))
        (PORT datab (1023:1023:1023) (1115:1115:1115))
        (PORT datac (818:818:818) (832:832:832))
        (PORT datad (1230:1230:1230) (1318:1318:1318))
        (IOPATH dataa combout (354:354:354) (349:349:349))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (992:992:992) (1074:1074:1074))
        (PORT clk (1850:1850:1850) (1877:1877:1877))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1790:1790:1790) (1853:1853:1853))
        (PORT d[1] (1887:1887:1887) (2021:2021:2021))
        (PORT d[2] (1608:1608:1608) (1709:1709:1709))
        (PORT d[3] (1632:1632:1632) (1742:1742:1742))
        (PORT d[4] (1524:1524:1524) (1625:1625:1625))
        (PORT d[5] (2401:2401:2401) (2545:2545:2545))
        (PORT d[6] (2503:2503:2503) (2622:2622:2622))
        (PORT d[7] (2588:2588:2588) (2697:2697:2697))
        (PORT d[8] (1980:1980:1980) (2028:2028:2028))
        (PORT d[9] (1981:1981:1981) (2022:2022:2022))
        (PORT d[10] (1519:1519:1519) (1597:1597:1597))
        (PORT d[11] (1746:1746:1746) (1790:1790:1790))
        (PORT d[12] (2596:2596:2596) (2752:2752:2752))
        (PORT clk (1847:1847:1847) (1873:1873:1873))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1848:1848:1848) (1857:1857:1857))
        (PORT clk (1847:1847:1847) (1873:1873:1873))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1850:1850:1850) (1877:1877:1877))
        (PORT d[0] (2373:2373:2373) (2394:2394:2394))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1851:1851:1851) (1878:1878:1878))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1851:1851:1851) (1878:1878:1878))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1851:1851:1851) (1878:1878:1878))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1851:1851:1851) (1878:1878:1878))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1498:1498:1498) (1545:1545:1545))
        (PORT d[1] (1536:1536:1536) (1610:1610:1610))
        (PORT d[2] (1582:1582:1582) (1643:1643:1643))
        (PORT d[3] (1510:1510:1510) (1589:1589:1589))
        (PORT d[4] (877:877:877) (884:884:884))
        (PORT d[5] (2765:2765:2765) (2798:2798:2798))
        (PORT d[6] (2865:2865:2865) (2979:2979:2979))
        (PORT d[7] (1192:1192:1192) (1225:1225:1225))
        (PORT d[8] (1157:1157:1157) (1169:1169:1169))
        (PORT d[9] (2318:2318:2318) (2433:2433:2433))
        (PORT d[10] (1731:1731:1731) (1787:1787:1787))
        (PORT d[11] (2835:2835:2835) (2990:2990:2990))
        (PORT d[12] (2314:2314:2314) (2446:2446:2446))
        (PORT clk (1811:1811:1811) (1804:1804:1804))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1811:1811:1811) (1804:1804:1804))
        (PORT d[0] (1278:1278:1278) (1220:1220:1220))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1812:1812:1812) (1805:1805:1805))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1812:1812:1812) (1805:1805:1805))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a21.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1812:1812:1812) (1805:1805:1805))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[5\]\~9)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1260:1260:1260) (1361:1361:1361))
        (PORT datab (1019:1019:1019) (1109:1109:1109))
        (PORT datac (1374:1374:1374) (1387:1387:1387))
        (PORT datad (1072:1072:1072) (1082:1082:1082))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH datab combout (342:342:342) (318:318:318))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[5\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1179:1179:1179) (1268:1268:1268))
        (PORT datab (199:199:199) (238:238:238))
        (PORT datac (172:172:172) (205:205:205))
        (PORT datad (1093:1093:1093) (1137:1137:1137))
        (IOPATH dataa combout (325:325:325) (328:328:328))
        (IOPATH datab combout (304:304:304) (308:308:308))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (990:990:990) (1050:1050:1050))
        (PORT clk (1852:1852:1852) (1879:1879:1879))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2276:2276:2276) (2330:2330:2330))
        (PORT d[1] (1675:1675:1675) (1819:1819:1819))
        (PORT d[2] (1871:1871:1871) (1973:1973:1973))
        (PORT d[3] (1647:1647:1647) (1763:1763:1763))
        (PORT d[4] (1540:1540:1540) (1619:1619:1619))
        (PORT d[5] (2369:2369:2369) (2507:2507:2507))
        (PORT d[6] (3054:3054:3054) (3164:3164:3164))
        (PORT d[7] (2552:2552:2552) (2650:2650:2650))
        (PORT d[8] (1688:1688:1688) (1757:1757:1757))
        (PORT d[9] (1667:1667:1667) (1714:1714:1714))
        (PORT d[10] (1525:1525:1525) (1602:1602:1602))
        (PORT d[11] (1533:1533:1533) (1572:1572:1572))
        (PORT d[12] (2880:2880:2880) (3012:3012:3012))
        (PORT clk (1849:1849:1849) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1794:1794:1794) (1804:1804:1804))
        (PORT clk (1849:1849:1849) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1879:1879:1879))
        (PORT d[0] (2328:2328:2328) (2334:2334:2334))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1853:1853:1853) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1853:1853:1853) (1880:1880:1880))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1853:1853:1853) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1853:1853:1853) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1776:1776:1776) (1817:1817:1817))
        (PORT d[1] (1225:1225:1225) (1286:1286:1286))
        (PORT d[2] (1288:1288:1288) (1342:1342:1342))
        (PORT d[3] (1610:1610:1610) (1759:1759:1759))
        (PORT d[4] (2634:2634:2634) (2750:2750:2750))
        (PORT d[5] (2243:2243:2243) (2306:2306:2306))
        (PORT d[6] (2604:2604:2604) (2723:2723:2723))
        (PORT d[7] (1441:1441:1441) (1461:1461:1461))
        (PORT d[8] (1115:1115:1115) (1135:1135:1135))
        (PORT d[9] (2056:2056:2056) (2178:2178:2178))
        (PORT d[10] (1462:1462:1462) (1519:1519:1519))
        (PORT d[11] (2834:2834:2834) (2989:2989:2989))
        (PORT d[12] (2841:2841:2841) (2954:2954:2954))
        (PORT clk (1813:1813:1813) (1806:1806:1806))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1813:1813:1813) (1806:1806:1806))
        (PORT d[0] (760:760:760) (715:715:715))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1814:1814:1814) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1814:1814:1814) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a20.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1814:1814:1814) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[4\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1257:1257:1257) (1357:1357:1357))
        (PORT datab (1025:1025:1025) (1117:1117:1117))
        (PORT datac (1348:1348:1348) (1390:1390:1390))
        (PORT datad (1100:1100:1100) (1118:1118:1118))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH datab combout (342:342:342) (318:318:318))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (987:987:987) (1057:1057:1057))
        (PORT clk (1854:1854:1854) (1881:1881:1881))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2261:2261:2261) (2322:2322:2322))
        (PORT d[1] (1628:1628:1628) (1764:1764:1764))
        (PORT d[2] (1882:1882:1882) (2001:2001:2001))
        (PORT d[3] (1372:1372:1372) (1488:1488:1488))
        (PORT d[4] (1533:1533:1533) (1613:1613:1613))
        (PORT d[5] (2372:2372:2372) (2543:2543:2543))
        (PORT d[6] (2035:2035:2035) (2149:2149:2149))
        (PORT d[7] (2372:2372:2372) (2497:2497:2497))
        (PORT d[8] (1708:1708:1708) (1782:1782:1782))
        (PORT d[9] (1656:1656:1656) (1721:1721:1721))
        (PORT d[10] (2091:2091:2091) (2187:2187:2187))
        (PORT d[11] (1521:1521:1521) (1551:1551:1551))
        (PORT d[12] (2563:2563:2563) (2700:2700:2700))
        (PORT clk (1851:1851:1851) (1877:1877:1877))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1729:1729:1729) (1695:1695:1695))
        (PORT clk (1851:1851:1851) (1877:1877:1877))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1854:1854:1854) (1881:1881:1881))
        (PORT d[0] (2254:2254:2254) (2232:2232:2232))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1855:1855:1855) (1882:1882:1882))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1855:1855:1855) (1882:1882:1882))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1855:1855:1855) (1882:1882:1882))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1855:1855:1855) (1882:1882:1882))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1784:1784:1784) (1839:1839:1839))
        (PORT d[1] (1480:1480:1480) (1552:1552:1552))
        (PORT d[2] (1288:1288:1288) (1342:1342:1342))
        (PORT d[3] (982:982:982) (1070:1070:1070))
        (PORT d[4] (2655:2655:2655) (2774:2774:2774))
        (PORT d[5] (2243:2243:2243) (2306:2306:2306))
        (PORT d[6] (2577:2577:2577) (2690:2690:2690))
        (PORT d[7] (869:869:869) (896:896:896))
        (PORT d[8] (1498:1498:1498) (1530:1530:1530))
        (PORT d[9] (2350:2350:2350) (2439:2439:2439))
        (PORT d[10] (1434:1434:1434) (1487:1487:1487))
        (PORT d[11] (2517:2517:2517) (2573:2573:2573))
        (PORT d[12] (2329:2329:2329) (2446:2446:2446))
        (PORT clk (1815:1815:1815) (1808:1808:1808))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1815:1815:1815) (1808:1808:1808))
        (PORT d[0] (542:542:542) (517:517:517))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1816:1816:1816) (1809:1809:1809))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1816:1816:1816) (1809:1809:1809))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a4.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1816:1816:1816) (1809:1809:1809))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1312:1312:1312) (1378:1378:1378))
        (PORT clk (1856:1856:1856) (1883:1883:1883))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1469:1469:1469) (1531:1531:1531))
        (PORT d[1] (1615:1615:1615) (1744:1744:1744))
        (PORT d[2] (1893:1893:1893) (1995:1995:1995))
        (PORT d[3] (1586:1586:1586) (1700:1700:1700))
        (PORT d[4] (1771:1771:1771) (1836:1836:1836))
        (PORT d[5] (2897:2897:2897) (3047:3047:3047))
        (PORT d[6] (3625:3625:3625) (3741:3741:3741))
        (PORT d[7] (2419:2419:2419) (2536:2536:2536))
        (PORT d[8] (1434:1434:1434) (1498:1498:1498))
        (PORT d[9] (1346:1346:1346) (1392:1392:1392))
        (PORT d[10] (1809:1809:1809) (1906:1906:1906))
        (PORT d[11] (1828:1828:1828) (1862:1862:1862))
        (PORT d[12] (2275:2275:2275) (2408:2408:2408))
        (PORT clk (1853:1853:1853) (1879:1879:1879))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1504:1504:1504) (1474:1474:1474))
        (PORT clk (1853:1853:1853) (1879:1879:1879))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1856:1856:1856) (1883:1883:1883))
        (PORT d[0] (2029:2029:2029) (2011:2011:2011))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1857:1857:1857) (1884:1884:1884))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1857:1857:1857) (1884:1884:1884))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1857:1857:1857) (1884:1884:1884))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1857:1857:1857) (1884:1884:1884))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2103:2103:2103) (2171:2171:2171))
        (PORT d[1] (1480:1480:1480) (1580:1580:1580))
        (PORT d[2] (1145:1145:1145) (1192:1192:1192))
        (PORT d[3] (931:931:931) (1012:1012:1012))
        (PORT d[4] (2627:2627:2627) (2739:2739:2739))
        (PORT d[5] (2261:2261:2261) (2323:2323:2323))
        (PORT d[6] (2572:2572:2572) (2681:2681:2681))
        (PORT d[7] (2055:2055:2055) (2159:2159:2159))
        (PORT d[8] (1479:1479:1479) (1510:1510:1510))
        (PORT d[9] (2052:2052:2052) (2171:2171:2171))
        (PORT d[10] (1456:1456:1456) (1508:1508:1508))
        (PORT d[11] (2552:2552:2552) (2690:2690:2690))
        (PORT d[12] (2054:2054:2054) (2175:2175:2175))
        (PORT clk (1817:1817:1817) (1810:1810:1810))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1817:1817:1817) (1810:1810:1810))
        (PORT d[0] (786:786:786) (761:761:761))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1818:1818:1818) (1811:1811:1811))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1818:1818:1818) (1811:1811:1811))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a12.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1818:1818:1818) (1811:1811:1811))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[4\]\~11)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1252:1252:1252) (1352:1352:1352))
        (PORT datab (1028:1028:1028) (1114:1114:1114))
        (PORT datac (1354:1354:1354) (1377:1377:1377))
        (PORT datad (1387:1387:1387) (1400:1400:1400))
        (IOPATH dataa combout (337:337:337) (338:338:338))
        (IOPATH datab combout (337:337:337) (348:348:348))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[4\]\~13)
    (DELAY
      (ABSOLUTE
        (PORT dataa (201:201:201) (246:246:246))
        (PORT datab (201:201:201) (241:241:241))
        (PORT datac (1142:1142:1142) (1225:1225:1225))
        (PORT datad (1094:1094:1094) (1137:1137:1137))
        (IOPATH dataa combout (303:303:303) (299:299:299))
        (IOPATH datab combout (304:304:304) (308:308:308))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2079:2079:2079) (2163:2163:2163))
        (PORT clk (1847:1847:1847) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2236:2236:2236) (2347:2347:2347))
        (PORT d[1] (2042:2042:2042) (2262:2262:2262))
        (PORT d[2] (2351:2351:2351) (2507:2507:2507))
        (PORT d[3] (1600:1600:1600) (1732:1732:1732))
        (PORT d[4] (1709:1709:1709) (1803:1803:1803))
        (PORT d[5] (1768:1768:1768) (1876:1876:1876))
        (PORT d[6] (1717:1717:1717) (1834:1834:1834))
        (PORT d[7] (1715:1715:1715) (1761:1761:1761))
        (PORT d[8] (1469:1469:1469) (1545:1545:1545))
        (PORT d[9] (1910:1910:1910) (1962:1962:1962))
        (PORT d[10] (1762:1762:1762) (1830:1830:1830))
        (PORT d[11] (2478:2478:2478) (2509:2509:2509))
        (PORT d[12] (2292:2292:2292) (2446:2446:2446))
        (PORT clk (1844:1844:1844) (1871:1871:1871))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1933:1933:1933) (1907:1907:1907))
        (PORT clk (1844:1844:1844) (1871:1871:1871))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1847:1847:1847) (1875:1875:1875))
        (PORT d[0] (2458:2458:2458) (2444:2444:2444))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1848:1848:1848) (1876:1876:1876))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1848:1848:1848) (1876:1876:1876))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1848:1848:1848) (1876:1876:1876))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1848:1848:1848) (1876:1876:1876))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1861:1861:1861) (1929:1929:1929))
        (PORT d[1] (2177:2177:2177) (2305:2305:2305))
        (PORT d[2] (2077:2077:2077) (2190:2190:2190))
        (PORT d[3] (1613:1613:1613) (1740:1740:1740))
        (PORT d[4] (2674:2674:2674) (2775:2775:2775))
        (PORT d[5] (2612:2612:2612) (2708:2708:2708))
        (PORT d[6] (2554:2554:2554) (2664:2664:2664))
        (PORT d[7] (1477:1477:1477) (1490:1490:1490))
        (PORT d[8] (3118:3118:3118) (3226:3226:3226))
        (PORT d[9] (2731:2731:2731) (2875:2875:2875))
        (PORT d[10] (3336:3336:3336) (3420:3420:3420))
        (PORT d[11] (2329:2329:2329) (2466:2466:2466))
        (PORT d[12] (1202:1202:1202) (1249:1249:1249))
        (PORT clk (1808:1808:1808) (1802:1802:1802))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1808:1808:1808) (1802:1802:1802))
        (PORT d[0] (1964:1964:1964) (2025:2025:2025))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1809:1809:1809) (1803:1803:1803))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1809:1809:1809) (1803:1803:1803))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a11.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1809:1809:1809) (1803:1803:1803))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1790:1790:1790) (1892:1892:1892))
        (PORT clk (1845:1845:1845) (1873:1873:1873))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2590:2590:2590) (2716:2716:2716))
        (PORT d[1] (2013:2013:2013) (2224:2224:2224))
        (PORT d[2] (2353:2353:2353) (2503:2503:2503))
        (PORT d[3] (1893:1893:1893) (2024:2024:2024))
        (PORT d[4] (1742:1742:1742) (1842:1842:1842))
        (PORT d[5] (1774:1774:1774) (1878:1878:1878))
        (PORT d[6] (2526:2526:2526) (2654:2654:2654))
        (PORT d[7] (1971:1971:1971) (2008:2008:2008))
        (PORT d[8] (1707:1707:1707) (1777:1777:1777))
        (PORT d[9] (1937:1937:1937) (2013:2013:2013))
        (PORT d[10] (1769:1769:1769) (1852:1852:1852))
        (PORT d[11] (2195:2195:2195) (2219:2219:2219))
        (PORT d[12] (2336:2336:2336) (2492:2492:2492))
        (PORT clk (1842:1842:1842) (1869:1869:1869))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2189:2189:2189) (2206:2206:2206))
        (PORT clk (1842:1842:1842) (1869:1869:1869))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1845:1845:1845) (1873:1873:1873))
        (PORT d[0] (2714:2714:2714) (2743:2743:2743))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1846:1846:1846) (1874:1874:1874))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1846:1846:1846) (1874:1874:1874))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1846:1846:1846) (1874:1874:1874))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1846:1846:1846) (1874:1874:1874))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1848:1848:1848) (1936:1936:1936))
        (PORT d[1] (1906:1906:1906) (2057:2057:2057))
        (PORT d[2] (2093:2093:2093) (2188:2188:2188))
        (PORT d[3] (1626:1626:1626) (1737:1737:1737))
        (PORT d[4] (2977:2977:2977) (3080:3080:3080))
        (PORT d[5] (2885:2885:2885) (2980:2980:2980))
        (PORT d[6] (2557:2557:2557) (2667:2667:2667))
        (PORT d[7] (963:963:963) (1003:1003:1003))
        (PORT d[8] (3104:3104:3104) (3223:3223:3223))
        (PORT d[9] (2722:2722:2722) (2846:2846:2846))
        (PORT d[10] (3049:3049:3049) (3123:3123:3123))
        (PORT d[11] (2634:2634:2634) (2774:2774:2774))
        (PORT d[12] (943:943:943) (991:991:991))
        (PORT clk (1806:1806:1806) (1800:1800:1800))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1806:1806:1806) (1800:1800:1800))
        (PORT d[0] (1299:1299:1299) (1276:1276:1276))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1807:1807:1807) (1801:1801:1801))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1807:1807:1807) (1801:1801:1801))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a3.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1807:1807:1807) (1801:1801:1801))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[3\]\~14)
    (DELAY
      (ABSOLUTE
        (PORT dataa (880:880:880) (893:893:893))
        (PORT datab (1028:1028:1028) (1115:1115:1115))
        (PORT datac (613:613:613) (625:625:625))
        (PORT datad (1223:1223:1223) (1308:1308:1308))
        (IOPATH dataa combout (304:304:304) (299:299:299))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1536:1536:1536) (1640:1640:1640))
        (PORT clk (1841:1841:1841) (1869:1869:1869))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2270:2270:2270) (2397:2397:2397))
        (PORT d[1] (1969:1969:1969) (2175:2175:2175))
        (PORT d[2] (1812:1812:1812) (1940:1940:1940))
        (PORT d[3] (1926:1926:1926) (2056:2056:2056))
        (PORT d[4] (1995:1995:1995) (2084:2084:2084))
        (PORT d[5] (1767:1767:1767) (1851:1851:1851))
        (PORT d[6] (2223:2223:2223) (2352:2352:2352))
        (PORT d[7] (2019:2019:2019) (2074:2074:2074))
        (PORT d[8] (1747:1747:1747) (1816:1816:1816))
        (PORT d[9] (1958:1958:1958) (2014:2014:2014))
        (PORT d[10] (1773:1773:1773) (1859:1859:1859))
        (PORT d[11] (1668:1668:1668) (1720:1720:1720))
        (PORT d[12] (2020:2020:2020) (2156:2156:2156))
        (PORT clk (1838:1838:1838) (1865:1865:1865))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1951:1951:1951) (2006:2006:2006))
        (PORT clk (1838:1838:1838) (1865:1865:1865))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1841:1841:1841) (1869:1869:1869))
        (PORT d[0] (2476:2476:2476) (2543:2543:2543))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1842:1842:1842) (1870:1870:1870))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1842:1842:1842) (1870:1870:1870))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1842:1842:1842) (1870:1870:1870))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1842:1842:1842) (1870:1870:1870))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1496:1496:1496) (1571:1571:1571))
        (PORT d[1] (1530:1530:1530) (1616:1616:1616))
        (PORT d[2] (1573:1573:1573) (1666:1666:1666))
        (PORT d[3] (1522:1522:1522) (1623:1623:1623))
        (PORT d[4] (2965:2965:2965) (3081:3081:3081))
        (PORT d[5] (2899:2899:2899) (3014:3014:3014))
        (PORT d[6] (2593:2593:2593) (2725:2725:2725))
        (PORT d[7] (1217:1217:1217) (1249:1249:1249))
        (PORT d[8] (3109:3109:3109) (3232:3232:3232))
        (PORT d[9] (2990:2990:2990) (3106:3106:3106))
        (PORT d[10] (3034:3034:3034) (3123:3123:3123))
        (PORT d[11] (2644:2644:2644) (2801:2801:2801))
        (PORT d[12] (1170:1170:1170) (1208:1208:1208))
        (PORT clk (1802:1802:1802) (1796:1796:1796))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1802:1802:1802) (1796:1796:1796))
        (PORT d[0] (1059:1059:1059) (1035:1035:1035))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1803:1803:1803) (1797:1797:1797))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1803:1803:1803) (1797:1797:1797))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a19.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1803:1803:1803) (1797:1797:1797))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[3\]\~15)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1256:1256:1256) (1367:1367:1367))
        (PORT datab (1025:1025:1025) (1114:1114:1114))
        (PORT datac (825:825:825) (837:837:837))
        (PORT datad (1066:1066:1066) (1072:1072:1072))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH datab combout (342:342:342) (318:318:318))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[3\]\~16)
    (DELAY
      (ABSOLUTE
        (PORT dataa (386:386:386) (412:412:412))
        (PORT datab (198:198:198) (237:237:237))
        (PORT datac (1148:1148:1148) (1228:1228:1228))
        (PORT datad (1093:1093:1093) (1137:1137:1137))
        (IOPATH dataa combout (303:303:303) (299:299:299))
        (IOPATH datab combout (304:304:304) (308:308:308))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1271:1271:1271) (1353:1353:1353))
        (PORT clk (1860:1860:1860) (1887:1887:1887))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2365:2365:2365) (2463:2463:2463))
        (PORT d[1] (1033:1033:1033) (1134:1134:1134))
        (PORT d[2] (1632:1632:1632) (1714:1714:1714))
        (PORT d[3] (1053:1053:1053) (1144:1144:1144))
        (PORT d[4] (1011:1011:1011) (1068:1068:1068))
        (PORT d[5] (983:983:983) (1038:1038:1038))
        (PORT d[6] (2560:2560:2560) (2689:2689:2689))
        (PORT d[7] (2769:2769:2769) (2907:2907:2907))
        (PORT d[8] (2293:2293:2293) (2353:2353:2353))
        (PORT d[9] (1033:1033:1033) (1098:1098:1098))
        (PORT d[10] (2127:2127:2127) (2249:2249:2249))
        (PORT d[11] (1553:1553:1553) (1623:1623:1623))
        (PORT d[12] (939:939:939) (968:968:968))
        (PORT clk (1857:1857:1857) (1883:1883:1883))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1230:1230:1230) (1212:1212:1212))
        (PORT clk (1857:1857:1857) (1883:1883:1883))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1860:1860:1860) (1887:1887:1887))
        (PORT d[0] (1755:1755:1755) (1749:1749:1749))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1579:1579:1579) (1647:1647:1647))
        (PORT d[1] (2046:2046:2046) (2131:2131:2131))
        (PORT d[2] (1343:1343:1343) (1387:1387:1387))
        (PORT d[3] (976:976:976) (1073:1073:1073))
        (PORT d[4] (2351:2351:2351) (2445:2445:2445))
        (PORT d[5] (1732:1732:1732) (1790:1790:1790))
        (PORT d[6] (1996:1996:1996) (2071:2071:2071))
        (PORT d[7] (1745:1745:1745) (1838:1838:1838))
        (PORT d[8] (2046:2046:2046) (2082:2082:2082))
        (PORT d[9] (1751:1751:1751) (1838:1838:1838))
        (PORT d[10] (1727:1727:1727) (1775:1775:1775))
        (PORT d[11] (2255:2255:2255) (2368:2368:2368))
        (PORT d[12] (2035:2035:2035) (2105:2105:2105))
        (PORT clk (1821:1821:1821) (1814:1814:1814))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1821:1821:1821) (1814:1814:1814))
        (PORT d[0] (1083:1083:1083) (1066:1066:1066))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1815:1815:1815))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1815:1815:1815))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a18.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1815:1815:1815))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[2\]\~18)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1002:1002:1002) (1103:1103:1103))
        (PORT datab (1157:1157:1157) (1198:1198:1198))
        (PORT datac (1007:1007:1007) (1105:1105:1105))
        (PORT datad (870:870:870) (869:869:869))
        (IOPATH dataa combout (327:327:327) (347:347:347))
        (IOPATH datab combout (331:331:331) (342:342:342))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1259:1259:1259) (1369:1369:1369))
        (PORT clk (1860:1860:1860) (1888:1888:1888))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2376:2376:2376) (2457:2457:2457))
        (PORT d[1] (1362:1362:1362) (1452:1452:1452))
        (PORT d[2] (1294:1294:1294) (1358:1358:1358))
        (PORT d[3] (748:748:748) (816:816:816))
        (PORT d[4] (711:711:711) (749:749:749))
        (PORT d[5] (683:683:683) (718:718:718))
        (PORT d[6] (680:680:680) (716:716:716))
        (PORT d[7] (693:693:693) (727:727:727))
        (PORT d[8] (659:659:659) (690:690:690))
        (PORT d[9] (1619:1619:1619) (1694:1694:1694))
        (PORT d[10] (720:720:720) (738:738:738))
        (PORT d[11] (1833:1833:1833) (1898:1898:1898))
        (PORT d[12] (692:692:692) (731:731:731))
        (PORT clk (1857:1857:1857) (1884:1884:1884))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (947:947:947) (903:903:903))
        (PORT clk (1857:1857:1857) (1884:1884:1884))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1860:1860:1860) (1888:1888:1888))
        (PORT d[0] (1472:1472:1472) (1440:1440:1440))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1889:1889:1889))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1889:1889:1889))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1889:1889:1889))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1889:1889:1889))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1826:1826:1826) (1881:1881:1881))
        (PORT d[1] (1793:1793:1793) (1874:1874:1874))
        (PORT d[2] (1603:1603:1603) (1659:1659:1659))
        (PORT d[3] (1257:1257:1257) (1377:1377:1377))
        (PORT d[4] (2043:2043:2043) (2116:2116:2116))
        (PORT d[5] (1991:1991:1991) (2076:2076:2076))
        (PORT d[6] (1419:1419:1419) (1476:1476:1476))
        (PORT d[7] (1718:1718:1718) (1794:1794:1794))
        (PORT d[8] (2023:2023:2023) (2055:2055:2055))
        (PORT d[9] (1998:1998:1998) (2095:2095:2095))
        (PORT d[10] (1786:1786:1786) (1836:1836:1836))
        (PORT d[11] (1918:1918:1918) (1971:1971:1971))
        (PORT d[12] (1449:1449:1449) (1518:1518:1518))
        (PORT clk (1821:1821:1821) (1815:1815:1815))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1821:1821:1821) (1815:1815:1815))
        (PORT d[0] (1097:1097:1097) (1117:1117:1117))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1816:1816:1816))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1816:1816:1816))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a10.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1816:1816:1816))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1538:1538:1538) (1639:1639:1639))
        (PORT clk (1858:1858:1858) (1886:1886:1886))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2338:2338:2338) (2429:2429:2429))
        (PORT d[1] (987:987:987) (1059:1059:1059))
        (PORT d[2] (1012:1012:1012) (1092:1092:1092))
        (PORT d[3] (1311:1311:1311) (1389:1389:1389))
        (PORT d[4] (994:994:994) (1046:1046:1046))
        (PORT d[5] (966:966:966) (1016:1016:1016))
        (PORT d[6] (985:985:985) (1038:1038:1038))
        (PORT d[7] (3036:3036:3036) (3192:3192:3192))
        (PORT d[8] (2606:2606:2606) (2686:2686:2686))
        (PORT d[9] (1019:1019:1019) (1057:1057:1057))
        (PORT d[10] (989:989:989) (1032:1032:1032))
        (PORT d[11] (1868:1868:1868) (1959:1959:1959))
        (PORT d[12] (1010:1010:1010) (1047:1047:1047))
        (PORT clk (1855:1855:1855) (1882:1882:1882))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1506:1506:1506) (1436:1436:1436))
        (PORT clk (1855:1855:1855) (1882:1882:1882))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1858:1858:1858) (1886:1886:1886))
        (PORT d[0] (2031:2031:2031) (1973:1973:1973))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1859:1859:1859) (1887:1887:1887))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1859:1859:1859) (1887:1887:1887))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1859:1859:1859) (1887:1887:1887))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1859:1859:1859) (1887:1887:1887))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1577:1577:1577) (1631:1631:1631))
        (PORT d[1] (1214:1214:1214) (1318:1318:1318))
        (PORT d[2] (1614:1614:1614) (1686:1686:1686))
        (PORT d[3] (1226:1226:1226) (1335:1335:1335))
        (PORT d[4] (1748:1748:1748) (1802:1802:1802))
        (PORT d[5] (1781:1781:1781) (1817:1817:1817))
        (PORT d[6] (1658:1658:1658) (1718:1718:1718))
        (PORT d[7] (1756:1756:1756) (1855:1855:1855))
        (PORT d[8] (1991:1991:1991) (2038:2038:2038))
        (PORT d[9] (1697:1697:1697) (1769:1769:1769))
        (PORT d[10] (1718:1718:1718) (1799:1799:1799))
        (PORT d[11] (1660:1660:1660) (1730:1730:1730))
        (PORT d[12] (1721:1721:1721) (1808:1808:1808))
        (PORT clk (1819:1819:1819) (1813:1813:1813))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1819:1819:1819) (1813:1813:1813))
        (PORT d[0] (1686:1686:1686) (1711:1711:1711))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1820:1820:1820) (1814:1814:1814))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1820:1820:1820) (1814:1814:1814))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a2.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1820:1820:1820) (1814:1814:1814))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[2\]\~17)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1010:1010:1010) (1110:1110:1110))
        (PORT datab (1170:1170:1170) (1184:1184:1184))
        (PORT datac (1013:1013:1013) (1113:1113:1113))
        (PORT datad (1425:1425:1425) (1427:1427:1427))
        (IOPATH dataa combout (339:339:339) (367:367:367))
        (IOPATH datab combout (344:344:344) (369:369:369))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[2\]\~19)
    (DELAY
      (ABSOLUTE
        (PORT dataa (913:913:913) (973:973:973))
        (PORT datab (751:751:751) (853:853:853))
        (PORT datac (173:173:173) (206:206:206))
        (PORT datad (173:173:173) (199:199:199))
        (IOPATH dataa combout (341:341:341) (319:319:319))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (985:985:985) (1069:1069:1069))
        (PORT clk (1860:1860:1860) (1887:1887:1887))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1159:1159:1159) (1216:1216:1216))
        (PORT d[1] (1930:1930:1930) (2043:2043:2043))
        (PORT d[2] (1619:1619:1619) (1723:1723:1723))
        (PORT d[3] (1322:1322:1322) (1412:1412:1412))
        (PORT d[4] (1257:1257:1257) (1318:1318:1318))
        (PORT d[5] (1013:1013:1013) (1075:1075:1075))
        (PORT d[6] (2304:2304:2304) (2439:2439:2439))
        (PORT d[7] (2407:2407:2407) (2539:2539:2539))
        (PORT d[8] (1952:1952:1952) (2008:2008:2008))
        (PORT d[9] (1021:1021:1021) (1060:1060:1060))
        (PORT d[10] (2122:2122:2122) (2240:2240:2240))
        (PORT d[11] (1565:1565:1565) (1614:1614:1614))
        (PORT d[12] (2598:2598:2598) (2758:2758:2758))
        (PORT clk (1857:1857:1857) (1883:1883:1883))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1456:1456:1456) (1406:1406:1406))
        (PORT clk (1857:1857:1857) (1883:1883:1883))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1860:1860:1860) (1887:1887:1887))
        (PORT d[0] (1981:1981:1981) (1943:1943:1943))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1598:1598:1598) (1654:1654:1654))
        (PORT d[1] (1806:1806:1806) (1875:1875:1875))
        (PORT d[2] (1291:1291:1291) (1344:1344:1344))
        (PORT d[3] (1239:1239:1239) (1290:1290:1290))
        (PORT d[4] (2364:2364:2364) (2434:2434:2434))
        (PORT d[5] (1926:1926:1926) (1974:1974:1974))
        (PORT d[6] (2289:2289:2289) (2380:2380:2380))
        (PORT d[7] (1783:1783:1783) (1894:1894:1894))
        (PORT d[8] (1790:1790:1790) (1832:1832:1832))
        (PORT d[9] (1765:1765:1765) (1867:1867:1867))
        (PORT d[10] (1496:1496:1496) (1536:1536:1536))
        (PORT d[11] (2238:2238:2238) (2297:2297:2297))
        (PORT d[12] (1765:1765:1765) (1866:1866:1866))
        (PORT clk (1821:1821:1821) (1814:1814:1814))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1821:1821:1821) (1814:1814:1814))
        (PORT d[0] (1092:1092:1092) (1077:1077:1077))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1815:1815:1815))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1815:1815:1815))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a1.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1815:1815:1815))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1047:1047:1047) (1132:1132:1132))
        (PORT clk (1859:1859:1859) (1886:1886:1886))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1778:1778:1778) (1842:1842:1842))
        (PORT d[1] (1899:1899:1899) (2034:2034:2034))
        (PORT d[2] (1608:1608:1608) (1694:1694:1694))
        (PORT d[3] (1359:1359:1359) (1457:1457:1457))
        (PORT d[4] (1774:1774:1774) (1854:1854:1854))
        (PORT d[5] (2610:2610:2610) (2754:2754:2754))
        (PORT d[6] (2277:2277:2277) (2406:2406:2406))
        (PORT d[7] (2433:2433:2433) (2569:2569:2569))
        (PORT d[8] (1967:1967:1967) (2021:2021:2021))
        (PORT d[9] (1360:1360:1360) (1428:1428:1428))
        (PORT d[10] (1260:1260:1260) (1323:1323:1323))
        (PORT d[11] (1245:1245:1245) (1293:1293:1293))
        (PORT d[12] (2587:2587:2587) (2740:2740:2740))
        (PORT clk (1856:1856:1856) (1882:1882:1882))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1464:1464:1464) (1427:1427:1427))
        (PORT clk (1856:1856:1856) (1882:1882:1882))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1859:1859:1859) (1886:1886:1886))
        (PORT d[0] (1989:1989:1989) (1964:1964:1964))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1860:1860:1860) (1887:1887:1887))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1860:1860:1860) (1887:1887:1887))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1860:1860:1860) (1887:1887:1887))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1860:1860:1860) (1887:1887:1887))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (935:935:935) (982:982:982))
        (PORT d[1] (1495:1495:1495) (1576:1576:1576))
        (PORT d[2] (1010:1010:1010) (1058:1058:1058))
        (PORT d[3] (658:658:658) (718:718:718))
        (PORT d[4] (2329:2329:2329) (2427:2427:2427))
        (PORT d[5] (1937:1937:1937) (1989:1989:1989))
        (PORT d[6] (2265:2265:2265) (2355:2355:2355))
        (PORT d[7] (1783:1783:1783) (1895:1895:1895))
        (PORT d[8] (1791:1791:1791) (1832:1832:1832))
        (PORT d[9] (1765:1765:1765) (1868:1868:1868))
        (PORT d[10] (1685:1685:1685) (1721:1721:1721))
        (PORT d[11] (2521:2521:2521) (2649:2649:2649))
        (PORT d[12] (2337:2337:2337) (2454:2454:2454))
        (PORT clk (1820:1820:1820) (1813:1813:1813))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1820:1820:1820) (1813:1813:1813))
        (PORT d[0] (1034:1034:1034) (996:996:996))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1821:1821:1821) (1814:1814:1814))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1821:1821:1821) (1814:1814:1814))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a9.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1821:1821:1821) (1814:1814:1814))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[1\]\~21)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1052:1052:1052) (1147:1147:1147))
        (PORT datab (1126:1126:1126) (1133:1133:1133))
        (PORT datac (975:975:975) (1067:1067:1067))
        (PORT datad (1153:1153:1153) (1173:1173:1173))
        (IOPATH dataa combout (371:371:371) (376:376:376))
        (IOPATH datab combout (355:355:355) (349:349:349))
        (IOPATH datac combout (241:241:241) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1012:1012:1012) (1100:1100:1100))
        (PORT clk (1860:1860:1860) (1887:1887:1887))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2043:2043:2043) (2138:2138:2138))
        (PORT d[1] (1030:1030:1030) (1134:1134:1134))
        (PORT d[2] (1631:1631:1631) (1713:1713:1713))
        (PORT d[3] (1554:1554:1554) (1639:1639:1639))
        (PORT d[4] (990:990:990) (1057:1057:1057))
        (PORT d[5] (1197:1197:1197) (1229:1229:1229))
        (PORT d[6] (1551:1551:1551) (1640:1640:1640))
        (PORT d[7] (2785:2785:2785) (2948:2948:2948))
        (PORT d[8] (1152:1152:1152) (1194:1194:1194))
        (PORT d[9] (1020:1020:1020) (1059:1059:1059))
        (PORT d[10] (2100:2100:2100) (2217:2217:2217))
        (PORT d[11] (1573:1573:1573) (1640:1640:1640))
        (PORT d[12] (2571:2571:2571) (2727:2727:2727))
        (PORT clk (1857:1857:1857) (1883:1883:1883))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1257:1257:1257) (1234:1234:1234))
        (PORT clk (1857:1857:1857) (1883:1883:1883))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1860:1860:1860) (1887:1887:1887))
        (PORT d[0] (1782:1782:1782) (1771:1771:1771))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1565:1565:1565) (1646:1646:1646))
        (PORT d[1] (1762:1762:1762) (1859:1859:1859))
        (PORT d[2] (1310:1310:1310) (1374:1374:1374))
        (PORT d[3] (1209:1209:1209) (1291:1291:1291))
        (PORT d[4] (2385:2385:2385) (2458:2458:2458))
        (PORT d[5] (1918:1918:1918) (1972:1972:1972))
        (PORT d[6] (2263:2263:2263) (2330:2330:2330))
        (PORT d[7] (1779:1779:1779) (1887:1887:1887))
        (PORT d[8] (2047:2047:2047) (2083:2083:2083))
        (PORT d[9] (1758:1758:1758) (1854:1854:1854))
        (PORT d[10] (1739:1739:1739) (1785:1785:1785))
        (PORT d[11] (2259:2259:2259) (2375:2375:2375))
        (PORT d[12] (1738:1738:1738) (1834:1834:1834))
        (PORT clk (1821:1821:1821) (1814:1814:1814))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1821:1821:1821) (1814:1814:1814))
        (PORT d[0] (1010:1010:1010) (993:993:993))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1815:1815:1815))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1815:1815:1815))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a17.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1815:1815:1815))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[1\]\~20)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1008:1008:1008) (1108:1108:1108))
        (PORT datab (1168:1168:1168) (1204:1204:1204))
        (PORT datac (1013:1013:1013) (1107:1107:1107))
        (PORT datad (1111:1111:1111) (1102:1102:1102))
        (IOPATH dataa combout (327:327:327) (347:347:347))
        (IOPATH datab combout (331:331:331) (342:342:342))
        (IOPATH datac combout (243:243:243) (242:242:242))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[1\]\~22)
    (DELAY
      (ABSOLUTE
        (PORT dataa (913:913:913) (972:972:972))
        (PORT datab (750:750:750) (853:853:853))
        (PORT datac (172:172:172) (205:205:205))
        (PORT datad (173:173:173) (199:199:199))
        (IOPATH dataa combout (350:350:350) (366:366:366))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[1\]\~23)
    (DELAY
      (ABSOLUTE
        (PORT dataa (201:201:201) (245:245:245))
        (PORT datab (750:750:750) (851:851:851))
        (PORT datac (1093:1093:1093) (1181:1181:1181))
        (PORT datad (694:694:694) (782:782:782))
        (IOPATH dataa combout (354:354:354) (349:349:349))
        (IOPATH datab combout (355:355:355) (349:349:349))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1332:1332:1332) (1445:1445:1445))
        (PORT clk (1860:1860:1860) (1888:1888:1888))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2057:2057:2057) (2129:2129:2129))
        (PORT d[1] (1349:1349:1349) (1463:1463:1463))
        (PORT d[2] (1324:1324:1324) (1387:1387:1387))
        (PORT d[3] (1066:1066:1066) (1139:1139:1139))
        (PORT d[4] (976:976:976) (1021:1021:1021))
        (PORT d[5] (1001:1001:1001) (1042:1042:1042))
        (PORT d[6] (2565:2565:2565) (2715:2715:2715))
        (PORT d[7] (2751:2751:2751) (2888:2888:2888))
        (PORT d[8] (2275:2275:2275) (2333:2333:2333))
        (PORT d[9] (995:995:995) (1031:1031:1031))
        (PORT d[10] (985:985:985) (1024:1024:1024))
        (PORT d[11] (1584:1584:1584) (1659:1659:1659))
        (PORT d[12] (2900:2900:2900) (3060:3060:3060))
        (PORT clk (1857:1857:1857) (1884:1884:1884))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (975:975:975) (926:926:926))
        (PORT clk (1857:1857:1857) (1884:1884:1884))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1860:1860:1860) (1888:1888:1888))
        (PORT d[0] (1500:1500:1500) (1463:1463:1463))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1889:1889:1889))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1889:1889:1889))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1889:1889:1889))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1889:1889:1889))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1294:1294:1294) (1350:1350:1350))
        (PORT d[1] (1778:1778:1778) (1873:1873:1873))
        (PORT d[2] (1307:1307:1307) (1371:1371:1371))
        (PORT d[3] (960:960:960) (1055:1055:1055))
        (PORT d[4] (2022:2022:2022) (2091:2091:2091))
        (PORT d[5] (1459:1459:1459) (1499:1499:1499))
        (PORT d[6] (1965:1965:1965) (2034:2034:2034))
        (PORT d[7] (1440:1440:1440) (1520:1520:1520))
        (PORT d[8] (1445:1445:1445) (1476:1476:1476))
        (PORT d[9] (1473:1473:1473) (1545:1545:1545))
        (PORT d[10] (1437:1437:1437) (1502:1502:1502))
        (PORT d[11] (1658:1658:1658) (1711:1711:1711))
        (PORT d[12] (1750:1750:1750) (1827:1827:1827))
        (PORT clk (1821:1821:1821) (1815:1815:1815))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1821:1821:1821) (1815:1815:1815))
        (PORT d[0] (1293:1293:1293) (1302:1302:1302))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1816:1816:1816))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1816:1816:1816))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a16.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1816:1816:1816))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[0\]\~24)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1046:1046:1046) (1147:1147:1147))
        (PORT datab (1158:1158:1158) (1198:1198:1198))
        (PORT datac (970:970:970) (1064:1064:1064))
        (PORT datad (1118:1118:1118) (1123:1123:1123))
        (IOPATH dataa combout (327:327:327) (347:347:347))
        (IOPATH datab combout (331:331:331) (342:342:342))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1711:1711:1711) (1868:1868:1868))
        (PORT clk (1852:1852:1852) (1879:1879:1879))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2184:2184:2184) (2306:2306:2306))
        (PORT d[1] (2627:2627:2627) (2890:2890:2890))
        (PORT d[2] (2992:2992:2992) (3173:3173:3173))
        (PORT d[3] (1006:1006:1006) (1094:1094:1094))
        (PORT d[4] (1116:1116:1116) (1136:1136:1136))
        (PORT d[5] (848:848:848) (879:879:879))
        (PORT d[6] (1610:1610:1610) (1707:1707:1707))
        (PORT d[7] (838:838:838) (860:860:860))
        (PORT d[8] (860:860:860) (879:879:879))
        (PORT d[9] (826:826:826) (847:847:847))
        (PORT d[10] (903:903:903) (922:922:922))
        (PORT d[11] (2836:2836:2836) (2918:2918:2918))
        (PORT d[12] (1959:1959:1959) (2016:2016:2016))
        (PORT clk (1849:1849:1849) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2528:2528:2528) (2509:2509:2509))
        (PORT clk (1849:1849:1849) (1875:1875:1875))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1852:1852:1852) (1879:1879:1879))
        (PORT d[0] (3053:3053:3053) (3046:3046:3046))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1853:1853:1853) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1853:1853:1853) (1880:1880:1880))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1853:1853:1853) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1853:1853:1853) (1880:1880:1880))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1788:1788:1788) (1852:1852:1852))
        (PORT d[1] (1554:1554:1554) (1667:1667:1667))
        (PORT d[2] (1857:1857:1857) (1954:1954:1954))
        (PORT d[3] (1884:1884:1884) (1998:1998:1998))
        (PORT d[4] (1747:1747:1747) (1808:1808:1808))
        (PORT d[5] (1942:1942:1942) (1997:1997:1997))
        (PORT d[6] (2162:2162:2162) (2228:2228:2228))
        (PORT d[7] (2054:2054:2054) (2160:2160:2160))
        (PORT d[8] (2481:2481:2481) (2559:2559:2559))
        (PORT d[9] (2012:2012:2012) (2100:2100:2100))
        (PORT d[10] (2115:2115:2115) (2165:2165:2165))
        (PORT d[11] (2028:2028:2028) (2118:2118:2118))
        (PORT d[12] (2044:2044:2044) (2135:2135:2135))
        (PORT clk (1813:1813:1813) (1806:1806:1806))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1813:1813:1813) (1806:1806:1806))
        (PORT d[0] (1338:1338:1338) (1377:1377:1377))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1814:1814:1814) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1814:1814:1814) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a8.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1814:1814:1814) (1807:1807:1807))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1577:1577:1577) (1680:1680:1680))
        (PORT clk (1860:1860:1860) (1887:1887:1887))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2335:2335:2335) (2411:2411:2411))
        (PORT d[1] (1341:1341:1341) (1429:1429:1429))
        (PORT d[2] (1030:1030:1030) (1101:1101:1101))
        (PORT d[3] (1004:1004:1004) (1048:1048:1048))
        (PORT d[4] (976:976:976) (1016:1016:1016))
        (PORT d[5] (986:986:986) (1016:1016:1016))
        (PORT d[6] (949:949:949) (977:977:977))
        (PORT d[7] (3078:3078:3078) (3241:3241:3241))
        (PORT d[8] (2580:2580:2580) (2637:2637:2637))
        (PORT d[9] (1008:1008:1008) (1052:1052:1052))
        (PORT d[10] (971:971:971) (1007:1007:1007))
        (PORT d[11] (1863:1863:1863) (1932:1932:1932))
        (PORT d[12] (993:993:993) (1037:1037:1037))
        (PORT clk (1857:1857:1857) (1883:1883:1883))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1693:1693:1693) (1616:1616:1616))
        (PORT clk (1857:1857:1857) (1883:1883:1883))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1860:1860:1860) (1887:1887:1887))
        (PORT d[0] (2218:2218:2218) (2153:2153:2153))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1861:1861:1861) (1888:1888:1888))
        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1586:1586:1586) (1664:1664:1664))
        (PORT d[1] (1492:1492:1492) (1577:1577:1577))
        (PORT d[2] (1612:1612:1612) (1683:1683:1683))
        (PORT d[3] (1286:1286:1286) (1380:1380:1380))
        (PORT d[4] (2013:2013:2013) (2073:2073:2073))
        (PORT d[5] (1980:1980:1980) (2039:2039:2039))
        (PORT d[6] (1678:1678:1678) (1718:1718:1718))
        (PORT d[7] (1753:1753:1753) (1832:1832:1832))
        (PORT d[8] (1707:1707:1707) (1734:1734:1734))
        (PORT d[9] (1996:1996:1996) (2075:2075:2075))
        (PORT d[10] (2122:2122:2122) (2154:2154:2154))
        (PORT d[11] (1933:1933:1933) (1999:1999:1999))
        (PORT d[12] (1718:1718:1718) (1785:1785:1785))
        (PORT clk (1821:1821:1821) (1814:1814:1814))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (187:187:187))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1821:1821:1821) (1814:1814:1814))
        (PORT d[0] (1565:1565:1565) (1583:1583:1583))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1815:1815:1815))
        (IOPATH (posedge clk) pulse (0:0:0) (2479:2479:2479))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1815:1815:1815))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE mem\|mem_rtl_0\|auto_generated\|ram_block1a0.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1822:1822:1822) (1815:1815:1815))
        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[0\]\~25)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1046:1046:1046) (1146:1146:1146))
        (PORT datab (1082:1082:1082) (1093:1093:1093))
        (PORT datac (970:970:970) (1063:1063:1063))
        (PORT datad (1111:1111:1111) (1136:1136:1136))
        (IOPATH dataa combout (356:356:356) (368:368:368))
        (IOPATH datab combout (342:342:342) (318:318:318))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[0\]\~26)
    (DELAY
      (ABSOLUTE
        (PORT dataa (913:913:913) (973:973:973))
        (PORT datab (751:751:751) (851:851:851))
        (PORT datac (171:171:171) (205:205:205))
        (PORT datad (173:173:173) (199:199:199))
        (IOPATH dataa combout (350:350:350) (366:366:366))
        (IOPATH datab combout (365:365:365) (373:373:373))
        (IOPATH datac combout (243:243:243) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE driver\|PIXEL_COLOR_OUT\[0\]\~27)
    (DELAY
      (ABSOLUTE
        (PORT dataa (908:908:908) (989:989:989))
        (PORT datab (733:733:733) (820:820:820))
        (PORT datac (1096:1096:1096) (1180:1180:1180))
        (PORT datad (173:173:173) (199:199:199))
        (IOPATH dataa combout (354:354:354) (349:349:349))
        (IOPATH datab combout (381:381:381) (380:380:380))
        (IOPATH datac combout (241:241:241) (241:241:241))
        (IOPATH datad combout (130:130:130) (120:120:120))
      )
    )
  )
)
